公开(公告)号：US5717882A

公开(公告)日：1998-02-10

申请号：US764643

申请日：1996-12-11

申请人： Jeffrey M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  David B. Papworth ,  Michael A. Fetterman

发明人： Jeffrey M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  David B. Papworth ,  Michael A. Fetterman

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F9/00

CPC分类号： G06F9/30043 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836

摘要： A method and apparatus for performing operations with a processor in a computer system. Load operations are performed by use of a dispatch pipeline and a memory execution pipeline. The dispatch pipeline dispatches the load operation for execution by the processor, while the memory execution pipeline controls the execution of the load operation to memory. The present invention reduces the latency involved in executing a load operation by coupling the execution of the two pipelines during execution of the load operation.

摘要翻译： 一种用于使用计算机系统中的处理器执行操作的方法和装置。 通过使用调度管道和存储器执行管线来执行加载操作。 调度管道调度处理器执行的加载操作，而存储器执行流水线控制对存储器的加载操作的执行。 本发明通过在执行加载操作期间耦合两条管线的执行来减少执行加载操作所涉及的延迟。

公开(公告)号：US5588126A

公开(公告)日：1996-12-24

申请号：US446030

申请日：1995-05-19

申请人： Jeffrey M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  David B. Papworth

发明人： Jeffrey M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  David B. Papworth

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3834

摘要： In an out-of-order execution computer system, a store buffer is conditionally signaled to output buffered store data of buffered memory store operations, when a buffered memory load operation is being executed. The determination on whether to signal the store buffer or not is made using control information that includes the allocation state of the store buffer at the time the memory load operation being executed was issued. The allocation state includes the identification of the buffer slot storing the last memory store operation stored into the store buffer, and the wraparound state of a circular wraparound allocation approach employed to allocate buffer slots to the memory store operations, at the time the memory load operation being executed was issued.

摘要翻译： 在无序执行计算机系统中，当执行缓冲存储器加载操作时，存储缓冲器有条件地发信号通知缓冲存储器存储操作的缓冲存储数据。 使用包含在执行存储器加载操作的时刻存储缓冲器的分配状态的控制信息来确定是否发出存储缓冲器的信号。 分配状态包括存储存储到存储缓冲器中的最后存储器存储操作的缓冲器槽的标识，以及在存储器加载操作时用于将缓冲器时隙分配给存储器存储操作的循环环绕分配方法的环绕状态 正在执行中。

公开(公告)号：US5606670A

公开(公告)日：1997-02-25

申请号：US636173

申请日：1996-04-22

申请人： Jeffrey M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  David B. Papworth

发明人： Jeffrey M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  David B. Papworth

IPC分类号： G06F9/38 ,  G06F9/22

CPC分类号： G06F9/3834

摘要： Store forwarding circuitry is provided to an out-of-order execution processor having a store buffer of buffered memory store operations. The store forwarding circuitry conditionally forwards store data for a memory load operation from a variable subset of the buffered memory store operations that is functionally dependent on the time the memory load operation is issued, taking into account the execution states of these buffered memory store operations. The memory load operation may be issued speculatively and/or executed out-of-order. The execution states of the buffered memory store operations may be speculatively executed or committed. The data and address aspects of the memory store operations may be executed separately.

摘要翻译： 存储转发电路被提供给具有缓冲存储器存储操作的存储缓冲器的无序执行处理器。 考虑到这些缓冲存储器存储操作的执行状态，存储转发电路有条件地转发存储器加载操作的存储数据，该数据来自缓冲存储器存储操作的可变子集，该操作在功能上取决于发出存储器加载操作的时间。 存储器加载操作可以推测性地和/或无序地执行。 可以推测性地执行或提交缓冲存储器存储操作的执行状态。 存储器存储操作的数据和地址方面可以分开执行。

公开(公告)号：US5671444A

公开(公告)日：1997-09-23

申请号：US731545

申请日：1996-10-15

申请人： Haitham Akkary ,  Jeffrey M. Abramson ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  Mandar S. Joshi ,  Brent E. Lince

发明人： Haitham Akkary ,  Jeffrey M. Abramson ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  Mandar S. Joshi ,  Brent E. Lince

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0859 ,  G06F12/0831

摘要： A data cache and a plurality of companion fill buffers having corresponding tag matching circuitry are provided to a computer system. Each fill buffer independently stores and tracks a replacement cache line being filled with data returning from main memory in response to a cache miss. When the cache fill is completed, the replacement cache line is output for the cache tag and data arrays of the data cache if the memory locations are cacheable and the cache line has not been snoop hit while the cache fill was in progress. Additionally, the fill buffers are organized and provided with sufficient address and data ports as well as selectors to allow the fill buffers to respond to subsequent processor loads and stores, and external snoops that hit their cache lines while the cache fills are in progress. As a result, the cache tag and data arrays of the data cache can continue to serve subsequent processor loads and stores, and external snoops, while one or more cache fills are in progress, without ever having to stall the processor.

摘要翻译： 具有对应的标签匹配电路的数据高速缓存和多个伴随填充缓冲器被提供给计算机系统。 每个填充缓冲器独立地存储和跟踪填充有响应于高速缓存未命中从主存储器返回的数据的替换高速缓存行。 当缓存填充完成时，如果内存位置是可高速缓存的，并且缓存填充正在进行时，缓存线尚未被窥探，则会为高速缓存标签和数据高速缓存的数据阵列输出替换高速缓存行。 此外，填充缓冲区被组织并提供有足够的地址和数据端口以及选择器，以允许填充缓冲区响应后续处理器负载和存储，以及在高速缓存填充正在进行时触发其缓存行的外部监听。 因此，数据高速缓存的高速缓存标签和数据阵列可以在一个或多个缓存填充正在进行的同时继续提供后续的处理器加载和存储以及外部监听，而无需停止处理器。

公开(公告)号：US5748937A

公开(公告)日：1998-05-05

申请号：US825417

申请日：1997-03-28

申请人： Jeffrey M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland

发明人： Jeffrey M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland

IPC分类号： G06F9/38

CPC分类号： G06F9/3834

摘要： A computer system having a mechanism for maintaining processor ordering during out-of-order instruction execution is disclosed wherein load memory instructions are accessed according to program order and executed out-of-order in relation to the program order where appropriate. Processors in the system snoop an external bus for bus transactions that conflict with completed load memory instructions before committing results of the completed load memory instructions to an architectural state.

摘要翻译： 公开了一种具有用于在无序指令执行期间维持处理器排序的机构的计算机系统，其中根据程序顺序访问加载存储器指令，并且在适当时根据程序顺序执行无序操作。 在将完成的加载存储器指令的结果提交到架构状态之前，系统中的处理器会窥探总线事务的外部总线，这些总线事务与完成的加载存储器指令冲突。

公开(公告)号：US5680572A

公开(公告)日：1997-10-21

申请号：US680109

申请日：1996-07-15

申请人： Haitham Akkary ,  Jeffrey M. Abramson ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  Mandar S. Joshi ,  Brent E. Lince

发明人： Haitham Akkary ,  Jeffrey M. Abramson ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  Mandar S. Joshi ,  Brent E. Lince

IPC分类号： G06F12/08

CPC分类号： G06F12/0859

摘要： A data cache and a plurality of companion fill buffers having corresponding tag matching circuitry are provided to a computer system. Each fill buffer independently stores and tracks a replacement cache line being filled with data returning from main memory in response to a cache miss. When the cache fill is completed, the replacement cache line is output for the cache tag and data arrays of the data cache if the memory locations are cacheable and the cache line has not been snoop hit while the cache fill was in progress. Additionally, the fill buffers are organized and provided with sufficient address and data ports as well as selectors to allow the fill buffers to respond to subsequent processor loads and stores, and external snoops that hit their cache lines while the cache fills are in progress. As a result, the cache tag and data arrays of the data cache can continue to serve subsequent processor loads and stores, and external snoops, while one or more cache fills are in progress, without ever having to stall the processor.

摘要翻译： 具有对应的标签匹配电路的数据高速缓存和多个伴随填充缓冲器被提供给计算机系统。 每个填充缓冲器独立地存储和跟踪填充有响应于高速缓存未命中从主存储器返回的数据的替换高速缓存行。 当缓存填充完成时，如果内存位置是可高速缓存的，并且缓存填充正在进行时，缓存线尚未被窥探，则会为高速缓存标签和数据高速缓存的数据阵列输出替换高速缓存行。 此外，填充缓冲区被组织并提供有足够的地址和数据端口以及选择器，以允许填充缓冲区响应后续处理器负载和存储，以及在高速缓存填充正在进行时触发其缓存行的外部监听。 因此，数据高速缓存的高速缓存标签和数据阵列可以在一个或多个缓存填充正在进行的同时继续提供后续的处理器加载和存储以及外部监听，而无需停止处理器。

公开(公告)号：US5860154A

公开(公告)日：1999-01-12

申请号：US778969

申请日：1997-01-06

申请人： Jeffrey M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  Mark A. Timko

发明人： Jeffrey M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  Mark A. Timko

IPC分类号： G06F9/318 ,  G06F9/355 ,  G06F12/00

CPC分类号： G06F9/3555 ,  G06F9/3017

摘要： A macro instruction is provided for a microprocessor which allows a programmer to specify a base value, index, scale factor and displacement value for calculating an effective address and returning that result in a single clock cycle. The macro instruction is converted into a micro operation which is provided to the single-cycle execution unit with the required source operands for performing the calculation. Within the single-cycle execution unit, the index and scale factor are provided to a left shifter for multiplying the two values. The result of the left shift operation is added to the sum of the base and displacement. This results in the effective address which is then returned from the single-cycle execution unit to a predetermined destination. This provides for the calculation of an effective address in a single cycle pipeline execution unit that is independent of the memory system execution units.

摘要翻译： 为微处理器提供宏指令，允许程序员指定基值，索引，比例因子和位移值，用于计算有效地址并在单个时钟周期内返回该结果。 宏指令被转换为微操作，其被提供给具有用于执行计算的所需源操作数的单周期执行单元。 在单周期执行单元内，将索引和比例因子提供给用于乘以两个值的左移位器。 左移操作的结果被加到底座和位移之和上。 这导致有效地址然后从单周期执行单元返回到预定的目的地。 这提供了独立于存储器系统执行单元的单周期流水线执行单元中的有效地址的计算。

公开(公告)号：US5664137A

公开(公告)日：1997-09-02

申请号：US525499

申请日：1995-09-07

申请人： Jeffrey M. Abramson ,  Haitham Akkary ,  Atig A. Bajwa ,  Michael A. Fetterman ,  Andrew F. Glew ,  Glenn J. Hinton ,  Joel Huang ,  Kris G. Konigsfeld ,  Paul D. Madland ,  Prem Pahlajrai

发明人： Jeffrey M. Abramson ,  Haitham Akkary ,  Atig A. Bajwa ,  Michael A. Fetterman ,  Andrew F. Glew ,  Glenn J. Hinton ,  Joel Huang ,  Kris G. Konigsfeld ,  Paul D. Madland ,  Prem Pahlajrai

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3889 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857

摘要： A method and apparatus for performing store operations that includes calculating the address and obtaining the data for the store operation. The address represents the memory location to which the data is to be stored. Once the address is calculated and the data obtained, the store operation is committed to processor state. The store operation may be dispatched to memory to complete the execution of the store operation.

摘要翻译： 一种用于执行存储操作的方法和装置，包括计算地址并获得用于存储操作的数据。 地址表示要存储数据的存储器位置。 一旦计算了地址并获得了数据，存储操作就被提交到处理器状态。 可以将存储操作调度到存储器以完成存储操作的执行。

公开(公告)号：US5826109A

公开(公告)日：1998-10-20

申请号：US747197

申请日：1996-11-12

申请人： Jeffery M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  David B. Papworth ,  Robert W. Martell

发明人： Jeffery M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  David B. Papworth ,  Robert W. Martell

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F13/18

CPC分类号： G06F12/0859 ,  G06F9/3824 ,  G06F9/3834

摘要： The present invention provides for executing load instructions with a processor having a non-blocking cache memory, wherein individual load operations are dispatched to the cache memory and the cache memory signals the prevent the load operation from being sent to external memory when the load operation misses the cache memory and there is already a currently pending bus cycle to the same cache line. This helps reduce bus traffic on the external bus.

摘要翻译： 本发明提供用具有非阻塞高速缓冲存储器的处理器执行加载指令，其中单独的加载操作被分派到高速缓冲存储器，并且高速缓冲存储器发出信号，以防止当加载操作错过时将加载操作发送到外部存储器 高速缓存存储器并且已经存在当前待处理的总线周期到同一高速缓存行。 这有助于减少外部总线上的总线流量。

公开(公告)号：US5577200A

公开(公告)日：1996-11-19

申请号：US550573

申请日：1995-10-31

申请人： Jeffrey M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland

发明人： Jeffrey M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F12/04 ,  G06F11/00 ,  G06F9/00 ,  G06F9/30 ,  H01J1/00

CPC分类号： G06F9/30043 ,  G06F9/3816 ,  G06F9/3824 ,  G06F9/3834 ,  G06F12/04

摘要： A number of data misalignment detection circuits are provided to select ones of an execution unit and memory order interface components, of an out-of-order (OOO) execution computer system, this aids the buffering and fault generation circuits of the memory order interface components, to buffer and dispatch load and store operations depending on if the misalignments are detected and their nature, resulting in load and store operations of misaligned data against a memory subsystem of the OOO execution computer system are available, the data addressed by the load and store operations are of the following types: chunk split, cache split, or page split misaligned.

摘要翻译： 提供了多个数据未对准检测电路来选择一个执行单元和存储器顺序接口组件（一个执行计算机系统），这有助于存储器顺序接口组件的缓冲和故障产生电路 根据是否检测到未对齐状况来缓冲和调度加载和存储操作及其性质，从而导致对负责执行计算机系统的存储器子系统的未对齐数据的加载和存储操作可用，由加载和存储处理的数据 操作有以下类型：chunk split，cache split或页面拆分不对齐。