公开(公告)号：US5717882A

公开(公告)日：1998-02-10

申请号：US764643

申请日：1996-12-11

申请人： Jeffrey M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  David B. Papworth ,  Michael A. Fetterman

发明人： Jeffrey M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  David B. Papworth ,  Michael A. Fetterman

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F9/00

CPC分类号： G06F9/30043 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836

摘要： A method and apparatus for performing operations with a processor in a computer system. Load operations are performed by use of a dispatch pipeline and a memory execution pipeline. The dispatch pipeline dispatches the load operation for execution by the processor, while the memory execution pipeline controls the execution of the load operation to memory. The present invention reduces the latency involved in executing a load operation by coupling the execution of the two pipelines during execution of the load operation.

摘要翻译： 一种用于使用计算机系统中的处理器执行操作的方法和装置。 通过使用调度管道和存储器执行管线来执行加载操作。 调度管道调度处理器执行的加载操作，而存储器执行流水线控制对存储器的加载操作的执行。 本发明通过在执行加载操作期间耦合两条管线的执行来减少执行加载操作所涉及的延迟。

公开(公告)号：US5588126A

公开(公告)日：1996-12-24

申请号：US446030

申请日：1995-05-19

申请人： Jeffrey M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  David B. Papworth

发明人： Jeffrey M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  David B. Papworth

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3834

摘要： In an out-of-order execution computer system, a store buffer is conditionally signaled to output buffered store data of buffered memory store operations, when a buffered memory load operation is being executed. The determination on whether to signal the store buffer or not is made using control information that includes the allocation state of the store buffer at the time the memory load operation being executed was issued. The allocation state includes the identification of the buffer slot storing the last memory store operation stored into the store buffer, and the wraparound state of a circular wraparound allocation approach employed to allocate buffer slots to the memory store operations, at the time the memory load operation being executed was issued.

摘要翻译： 在无序执行计算机系统中，当执行缓冲存储器加载操作时，存储缓冲器有条件地发信号通知缓冲存储器存储操作的缓冲存储数据。 使用包含在执行存储器加载操作的时刻存储缓冲器的分配状态的控制信息来确定是否发出存储缓冲器的信号。 分配状态包括存储存储到存储缓冲器中的最后存储器存储操作的缓冲器槽的标识，以及在存储器加载操作时用于将缓冲器时隙分配给存储器存储操作的循环环绕分配方法的环绕状态 正在执行中。

公开(公告)号：US5606670A

公开(公告)日：1997-02-25

申请号：US636173

申请日：1996-04-22

申请人： Jeffrey M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  David B. Papworth

发明人： Jeffrey M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  David B. Papworth

IPC分类号： G06F9/38 ,  G06F9/22

CPC分类号： G06F9/3834

摘要： Store forwarding circuitry is provided to an out-of-order execution processor having a store buffer of buffered memory store operations. The store forwarding circuitry conditionally forwards store data for a memory load operation from a variable subset of the buffered memory store operations that is functionally dependent on the time the memory load operation is issued, taking into account the execution states of these buffered memory store operations. The memory load operation may be issued speculatively and/or executed out-of-order. The execution states of the buffered memory store operations may be speculatively executed or committed. The data and address aspects of the memory store operations may be executed separately.

摘要翻译： 存储转发电路被提供给具有缓冲存储器存储操作的存储缓冲器的无序执行处理器。 考虑到这些缓冲存储器存储操作的执行状态，存储转发电路有条件地转发存储器加载操作的存储数据，该数据来自缓冲存储器存储操作的可变子集，该操作在功能上取决于发出存储器加载操作的时间。 存储器加载操作可以推测性地和/或无序地执行。 可以推测性地执行或提交缓冲存储器存储操作的执行状态。 存储器存储操作的数据和地址方面可以分开执行。

公开(公告)号：US5826109A

公开(公告)日：1998-10-20

申请号：US747197

申请日：1996-11-12

申请人： Jeffery M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  David B. Papworth ,  Robert W. Martell

发明人： Jeffery M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  David B. Papworth ,  Robert W. Martell

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F13/18

CPC分类号： G06F12/0859 ,  G06F9/3824 ,  G06F9/3834

摘要： The present invention provides for executing load instructions with a processor having a non-blocking cache memory, wherein individual load operations are dispatched to the cache memory and the cache memory signals the prevent the load operation from being sent to external memory when the load operation misses the cache memory and there is already a currently pending bus cycle to the same cache line. This helps reduce bus traffic on the external bus.

摘要翻译： 本发明提供用具有非阻塞高速缓冲存储器的处理器执行加载指令，其中单独的加载操作被分派到高速缓冲存储器，并且高速缓冲存储器发出信号，以防止当加载操作错过时将加载操作发送到外部存储器 高速缓存存储器并且已经存在当前待处理的总线周期到同一高速缓存行。 这有助于减少外部总线上的总线流量。

公开(公告)号：US5751983A

公开(公告)日：1998-05-12

申请号：US538594

申请日：1995-10-03

申请人： Jeffrey M. Abramson ,  David B. Papworth ,  Haitham H. Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland

发明人： Jeffrey M. Abramson ,  David B. Papworth ,  Haitham H. Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland

IPC分类号： G06F9/38 ,  G06F3/38

CPC分类号： G06F9/3834

摘要： A method and apparatus for speculatively dispatching and/or executing LOADs in a computer system includes a memory subsystem of a out-of-order processor that handles LOAD and STORE operations by dispatching them to respective LOAD and STORE buffers in the memory subsystem. When a LOAD is subsequently dispatched for execution, the store buffer is searched for STOREs having unknown addresses. If any STOREs are found which are older than the dispatched LOAD, and which have an unknown address, the LOAD is tagged with an unknown STORE address identification (USAID). When a STORE is dispatched for execution, the LOAD buffer is searched for loads that have been denoted as mis-speculated loads. Mis-speculated loads are prevented from corrupting the architectural state of the machine with invalid data.

摘要翻译： 用于在计算机系统中推测调度和/或执行LOAD的方法和装置包括无序处理器的存储器子系统，其通过将它们分派到存储器子系统中的相应LOAD和STORE缓冲器来处理LOAD和STORE操作。 当随后调度LOAD进行执行时，搜索具有未知地址的STORE的存储缓冲区。 如果发现任何比发送的LOAD更旧的存储区，并且具有未知地址，则LOAD被标记为未知的存储地址标识（USAID）。 当调度STORE执行时，LOAD缓冲区将搜索已被表示为误推测负载的负载。 可以防止误导的负载破坏机器的无效数据的架构状态。

公开(公告)号：US5564111A

公开(公告)日：1996-10-08

申请号：US315833

申请日：1994-09-30

申请人： Andrew F. Glew ,  Haitham Akkary ,  Robert P. Colwell ,  Glenn J. Hinton ,  David B. Papworth ,  Michael A. Fetterman

发明人： Andrew F. Glew ,  Haitham Akkary ,  Robert P. Colwell ,  Glenn J. Hinton ,  David B. Papworth ,  Michael A. Fetterman

IPC分类号： G06F9/38 ,  G06F11/00 ,  G06F12/10 ,  G06F11/34

CPC分类号： G06F9/3865 ,  G06F11/0751 ,  G06F12/1027 ,  G06F9/3842 ,  G06F2212/684

摘要： A non-blocking translation lookaside buffer is described for use in a microprocessor capable of processing speculative and out-of-order instructions. Upon the detection of a fault, either during a translation lookaside buffer hit or a page table walk performed in response to a translation lookaside buffer miss, information associated with the faulting instruction is stored within a fault register within the translation lookaside buffer. The stored information includes the linear address of the instruction and information identifying the age of instruction. In addition to storing the information within the fault register, a portion of the information is transmitted to a reordering buffer of the microprocessor for storage therein pending retirement of the faulting instruction. Prior to retirement of the faulting instruction, the translation lookaside buffer continues to process further instructions. Upon retirement of each instruction, the reordering buffer determines whether a fault had been detected for that instruction and, if so, the microprocessor is flushed. Then, a branch is taken into microcode. The microcode accesses the linear address and other information stored within the fault register of the translation lookaside buffer and handles the fault. The system is flushed and the microcode is executed only for faulting instructions which actually retire. As such, faults detected while processing speculative instructions based upon mispredicted branches do not prevent further address translations and do not cause the system to be flushed. Method and apparatus implementations are described herein.

摘要翻译： 描述了用于能够处理推测和乱序指令的微处理器中的非阻塞转换后备缓冲器。 在检测到故障时，无论是在翻译后备缓冲器命中还是响应于翻译后备缓冲器未命中执行的页表行走期间，与故障指令相关联的信息都存储在翻译后备缓冲器内的故障寄存器内。 所存储的信息包括指令的线性地址和识别指令年龄的信息。 除了将信息存储在故障寄存器之外，信息的一部分被发送到微处理器的重排序缓冲器以便存储在故障指令中。 在故障指令退出之前，翻译后备缓冲区继续处理进一步的指令。 在每个指令退出后，重新排序缓冲器确定是否检测到该指令发生故障，如果是，则清除微处理器。 然后，一个分支被带入微码。 微代码访问存储在翻译后备缓冲区的故障寄存器内的线性地址和其他信息，并处理故障。 系统被刷新，微代码仅对实际退出的故障指令执行。 因此，基于错误预测的分支处理推测性指令时检测到的故障不会妨碍进一步的地址转换，并且不会导致系统被刷新。 本文描述了方法和装置实现。

公开(公告)号：US5584037A

公开(公告)日：1996-12-10

申请号：US571377

申请日：1995-12-13

申请人： David B. Papworth ,  Andrew F. Glew ,  Michael A. Fetterman ,  Glenn J. Hinton ,  Robert P. Colwell ,  Steven J. Griffith ,  Shantanu R. Gupta ,  Narayan Hegde

发明人： David B. Papworth ,  Andrew F. Glew ,  Michael A. Fetterman ,  Glenn J. Hinton ,  Robert P. Colwell ,  Steven J. Griffith ,  Shantanu R. Gupta ,  Narayan Hegde

IPC分类号： G06F5/10 ,  G06F5/14 ,  G06F9/38 ,  G06F12/00

CPC分类号： G06F5/14 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3844 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

摘要： An allocator assigns entries for a circular buffer. The allocator receives requests for storing data in entries of the circular buffer, and generates a head pointer to identify a starting entry in the circular buffer for which circular buffer entries are not allocated. In addition to pointing to an entry in the circular buffer, the head pointer includes a wrap bit. The allocator toggles the wrap bit each time the allocator traverses the linear queue of the circular buffer. A tail pointer is generated, including the wrap bit, to identify an ending entry in the circular buffer for which circular buffer entries are allocated. In response to the request for entries, the allocator sequentially assigns entries for the requests located between the head pointer and the tail pointer. The allocator has application for use in a microprocessor performing out-of-order dispatch and speculative execution. The allocator is coupled to a reorder buffer, configured as a circular buffer, to permit allocation of entries. The allocator utilizes an all or nothing allocation policy, such that either all or no incoming instructions are allocated during an allocation period.

摘要翻译： 分配器为循环缓冲区分配条目。 分配器接收在循环缓冲器的条目中存储数据的请求，并且生成头指针以标识不分配循环缓冲器条目的循环缓冲器中的起始条目。 除了指向循环缓冲区中的条目之外，头指针还包括一个换行位。 每次分配器遍历循环缓冲区的线性队列时，分配器将切换换行。 生成尾指针，包括换行位，以标识分配循环缓冲区条目的循环缓冲区中的结尾条目。 响应于条目请求，分配器顺序分配位于头部指针和尾部指针之间的请求的条目。 分配器具有用于执行无序调度和推测执行的微处理器的应用。 分配器被耦合到配置为循环缓冲器的重排序缓冲器，以允许分配条目。 分配器利用全部或全部分配策略，使得在分配周期期间分配全部或者没有传入指令。

公开(公告)号：US5471633A

公开(公告)日：1995-11-28

申请号：US205842

申请日：1994-03-01

申请人： Robert P. Colwell ,  Andrew F. Glew ,  David B. Papworth ,  Glenn J. Hinton ,  David W. Clift

发明人： Robert P. Colwell ,  Andrew F. Glew ,  David B. Papworth ,  Glenn J. Hinton ,  David W. Clift

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F7/00

CPC分类号： G06F9/3824 ,  G06F9/30112 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A register alias table unit (RAT) with an idiom recognition mechanism for overriding partial width conditions stalls is described. A partial width stall condition occurs during the RAT renaming process when a logical source register being renamed is larger than the corresponding physical source register pointed to by a renaming table. An idiom recognizer detects uops that zero their logical destination register and sets and clears zero bits in an iRAT array accordingly. The zero bits indicate which portions of an entry's physical source register are known to be zeros. A partial width stall override mechanism overrides a partial width stall condition when the zero bits for the physical source register causing the partial width stall indicate that the "missing" portion of the physical source register contains zeros. The performance of a microprocessor implementing such a RAT renaming mechanism with an idiom recognizer is improved because common partial width stalls are avoided.

摘要翻译： 描述了具有用于覆盖部分宽度条件失速的习惯识别机制的寄存器别名表单元（RAT）。 当重新命名的逻辑源寄存器大于重命名表指向的相应物理源寄存器时，在RAT重命名过程期间发生部分宽度失速状况。 成语识别器检测uops，使其逻辑目标寄存器为零，并相应地设置和清除iRAT阵列中的零位。 零位指示条目的物理源寄存器的哪些部分已知为零。 当导致部分宽度失速的物理源寄存器的零位指示物理源寄存器的“丢失”部分包含零时，部分宽度失速覆盖机制将覆盖部分宽度失速条件。 通过习惯识别器实现这种RAT重命名机构的微处理器的性能得到改善，因为避免了普通的部分宽度档位。

公开(公告)号：US5987600A

公开(公告)日：1999-11-16

申请号：US851140

申请日：1997-05-05

申请人： David B. Papworth ,  Glenn J. Hinton ,  Michael A. Fetterman ,  Robert P. Colwell ,  Andrew F. Glew

发明人： David B. Papworth ,  Glenn J. Hinton ,  Michael A. Fetterman ,  Robert P. Colwell ,  Andrew F. Glew

IPC分类号： G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3865 ,  G06F9/3842 ,  G06F9/3863

摘要： A method and circuitry for coordinating exceptions in a processor. The processor generates a result data value and an exception data value for each instruction wherein the exception data value specifies whether the corresponding instruction causes an exception. The processor commits the result data values to an architectural state of the processor in the sequential program order, and fetches an exception handler to processes the exception if the exception is indicated by one of the exception data values. The processor fetches an asynchronous event handler to processes an asynchronous event if the asynchronous event is detected while the result data values are committed to the architectural state of the processor.

摘要翻译： 用于协调处理器中的异常的方法和电路。 处理器为每个指令生成结果数据值和异常数据值，其中异常数据值指定相应指令是否引起异常。 处理器以顺序程序顺序将结果数据值提交给处理器的架构状态，并且如果异常由异常数据值之一指示，则提取异常处理程序来处理异常。 如果在结果数据值提交到处理器的架构状态时检测到异步事件，处理器将获取异步事件处理程序来处理异步事件。

公开(公告)号：US5627985A

公开(公告)日：1997-05-06

申请号：US177244

申请日：1994-01-04

申请人： Michael A. Fetterman ,  Andrew F. Glew ,  David B. Papworth ,  Glenn J. Hinton ,  Robert P. Colwell

发明人： Michael A. Fetterman ,  Andrew F. Glew ,  David B. Papworth ,  Glenn J. Hinton ,  Robert P. Colwell

IPC分类号： G06F9/38 ,  G06F9/34

CPC分类号： G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A speculative execution out of order processor comprising a reorder circuit containing a plurality of physical registers that buffer speculative execution results for integer and floating-point operations, and a real register circuit containing a plurality of committed state registers that buffer committed execution results for either integer or floating-point operations, depending on the register. The reorder and real register circuits read the speculative and committed source data values for incoming micro-ops, and transfer the speculative and committed source data values over to a micro-op dispatch circuit over a common data path. A retire logic circuit commits the speculative execution results to an architectural state by transferring the speculative execution results from the reorder circuit to the real register circuit.

摘要翻译： 一种推测执行乱序处理器，包括一个包含多个物理寄存器的重排序电路，该多个物理寄存器缓冲整数和浮点运算的推测执行结果，以及一个包含多个提交状态寄存器的实际寄存器电路，该寄存器电路缓冲任一整数的提交执行结果 或浮点运算，具体取决于寄存器。 重排序和实际寄存器电路读取输入微操作的推测和确定的源数据值，并通过公共数据路径将推测和承诺的源数据值传输到微操作调度电路。 退出逻辑电路通过将推测执行结果从重新排序电路传送到实际寄存器电路来将推测执行结果提交到架构状态。