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    Defect detection in semiconductor devices
    1.
    发明授权
    Defect detection in semiconductor devices 失效
    半导体器件缺陷检测

    公开(公告)号：US06686757B1

    公开(公告)日：2004-02-03

    申请号：US09409217

    申请日：1999-09-30

    申请人： Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis ,  Jeffrey D. Birdsley ,  Michael R. Bruce

    发明人： Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis ,  Jeffrey D. Birdsley ,  Michael R. Bruce

    IPC分类号： G01R3128

    CPC分类号： G01R31/311

    摘要： According to an example embodiment of the present invention, a defect detection approach involves detecting the existence of defects in an integrated circuit as a function of at least one applied energy source. In response to energy that is applied to the integrated circuit, response signals are detected. A parameter including information such as amplitude, frequency, phase, or a spectrum is developed for a reference integrated circuit device and then compared to the detected response signal. The deviation in the response and reference signals, and the type of energy source used, are correlated to a particular defect in the device.

    摘要翻译： 根据本发明的示例性实施例，缺陷检测方法包括检测作为至少一个应用能量源的函数的集成电路中的缺陷的存在。 响应于施加到集成电路的能量，检测响应信号。 为参考集成电路器件开发包括振幅，频率，相位或频谱等信息的参数，然后与检测到的响应信号进行比较。 响应和参考信号的偏差以及所使用的能量源的类型与设备中的特定缺陷相关。

    Quadrant avalanche photodiode time-resolved detection
    2.
    发明授权
    Quadrant avalanche photodiode time-resolved detection 失效
    象限雪崩光电二极管时间分辨检测

    公开(公告)号：US06483327B1

    公开(公告)日：2002-11-19

    申请号：US09409088

    申请日：1999-09-30

    申请人： Michael R. Bruce ,  Victoria J. Bruce ,  Jeffrey D. Birdsley ,  Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis

    发明人： Michael R. Bruce ,  Victoria J. Bruce ,  Jeffrey D. Birdsley ,  Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis

    IPC分类号： G01R31302

    CPC分类号： G01R1/071 ,  G01R31/311

    摘要： A method and system providing spatial and timing resolution for photoemission microscopy of an integrated circuit. A microscope having an objective lens forming a focal plane is arranged to view the integrated circuit, and an aperture element having an aperture is optically aligned in the back focal plane of the microscope. The aperture element is positioned for viewing a selected area of the integrated circuit. A position-sensitive avalanche photo-diode is optically aligned with the aperture to detect photoemissions when test signals are applied to the integrated circuit.

    摘要翻译： 一种为集成电路的光电显微镜提供空间和时序分辨率的方法和系统。 具有形成焦平面的物镜的显微镜被布置成观看集成电路，并且具有孔的孔径元件在显微镜的后焦平面中被光学对准。 光圈元件被定位成用于观看集成电路的选定区域。 位置敏感的雪崩光电二极管与孔径光学对准以在测试信号被施加到集成电路时检测光电发射。

    Acoustic 3D analysis of circuit structures
    3.
    发明授权
    Acoustic 3D analysis of circuit structures 失效
    电路结构的声学3D分析

    公开(公告)号：US06430728B1

    公开(公告)日：2002-08-06

    申请号：US09410147

    申请日：1999-09-30

    申请人： Rama R. Goruganthu ,  Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring

    发明人： Rama R. Goruganthu ,  Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring

    IPC分类号： G06F1750

    CPC分类号： G01R31/307 ,  G10K15/046

    摘要： According to an example embodiment, the present invention is directed to a system and method for analyzing an integrated circuit. A laser is directed to the back side of an integrated circuit and causes local heating, which generates acoustic energy in the circuit. The acoustic energy propagation in the integrated circuit is detected via at least two detectors. Using the detected acoustic energy from the detectors, at least one circuit defect is detected and located.

    摘要翻译： 根据示例性实施例，本发明涉及用于分析集成电路的系统和方法。 激光被引导到集成电路的背面，并引起局部加热，其在电路中产生声能。 通过至少两个检测器检测集成电路中的声能传播。 使用来自检测器的检测到的声能，检测和定位至少一个电路缺陷。

    Selective state change analysis of a SOI die
    4.
    发明授权
    Selective state change analysis of a SOI die 失效
    SOI裸片的选择状态变化分析

    公开(公告)号：US06414335B1

    公开(公告)日：2002-07-02

    申请号：US09864688

    申请日：2001-05-23

    申请人： Rama R. Goruganthu ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone ,  Jeffrey D. Birdsley

    发明人： Rama R. Goruganthu ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone ,  Jeffrey D. Birdsley

    IPC分类号： H01L2358

    CPC分类号： G01R31/312 ,  G01R31/307

    摘要： Analysis of a semiconductor die having silicon-on-insulator (SOI) structure is enhanced by capacitively coupling a signal to the die. According to an example embodiment of the present invention, a die having a thinned back side is analyzed by capacitively coupling an input signal through the insulator portion of the SOI structure and effecting a state change to circuitry in the die. The state change is used to evaluate a characteristic of the die, such as by detecting a response to the state change. The ability to force such a state change is helpful for evaluating dies having SOI structure, and is particularly useful for evaluation techniques that require or benefit from maintaining the insulator portion of the SOI structure intact.

    摘要翻译： 通过将信号电容耦合到管芯来增强具有绝缘体上硅（SOI）结构的半导体管芯的分析。 根据本发明的示例性实施例，通过电容耦合通过SOI结构的绝缘体部分的输入信号并对模具中的电路进行状态分析来分析具有减薄背侧的管芯。 状态变化用于评估管芯的特性，例如通过检测对状态变化的响应。 强制这种状态变化的能力有助于评估具有SOI结构的管芯，并且对于需要或受益于保持SOI结构的绝缘体部分而完整的评估技术特别有用。

    Magnetic resonance imaging of semiconductor devices
    6.
    发明授权
    Magnetic resonance imaging of semiconductor devices 失效
    半导体器件的磁共振成像

    公开(公告)号：US06529029B1

    公开(公告)日：2003-03-04

    申请号：US09409973

    申请日：1999-09-30

    申请人： Michael R. Bruce ,  Jeffrey D. Birdsley ,  Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis

    发明人： Michael R. Bruce ,  Jeffrey D. Birdsley ,  Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis

    IPC分类号： G01R3128

    CPC分类号： G01R31/303

    摘要： A method for detecting substrate damage in a flip chip die, having a back side and a circuit side, that uses magnetic resonance imaging. The back side of the die is first globally thinned down and a region for examination is selected. A magnetic field is applied to the selected region and then the region is scanned with a magnetic resonance imaging arrangement. A plurality of perturbations are measured to generate an array of perturbation signals, which are then converted to a local susceptibility map of the selected region of the die. The susceptibility map of the selected region is then examined to determine if there is any substrate damage.

    摘要翻译： 一种用于检测使用磁共振成像的具有背面和电路侧的倒装芯片的基板损伤的方法。 首先将模具的背面全局变薄，并选择检查区域。 将磁场施加到所选择的区域，然后用磁共振成像装置扫描该区域。 测量多个扰动以产生扰动信号阵列，然后将它们转换成所选择的模具区域的局部磁敏度图。 然后检查所选区域的磁敏度图，以确定是否存在任何底物损伤。

    Forming elongated probe points useful in testing semiconductor devices
    7.
    发明授权
    Forming elongated probe points useful in testing semiconductor devices 失效
    形成可用于测试半导体器件的细长探针点

    公开(公告)号：US06372529B1

    公开(公告)日：2002-04-16

    申请号：US09408616

    申请日：1999-09-30

    申请人： Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis ,  Jeffrey D. Birdsley ,  Michael R. Bruce

    发明人： Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis ,  Jeffrey D. Birdsley ,  Michael R. Bruce

    IPC分类号： G01R3126

    CPC分类号： G01R31/31905 ,  G01R3/00 ,  G01R31/2884

    摘要： Access to portions of semiconductor devices is enhanced via a method and system for probing between circuitry in the semiconductor device during post-manufacture analysis of the semiconductor device. According to an example embodiment of the present invention, an elongated conductive via probe is formed in a semiconductor device having circuitry in a circuit side opposite a back side. The probe is formed by first removing substrate from the semiconductor device and forming an exposed region over a target node between circuitry in the device. A narrow conductor is then formed for accessing the target node, with the conductor and extending between the circuitry and into the back side and forming the elongated conductive via probe. The probe is accessed and used for analyzing the device. In this manner, access to a difficult-to-reach target node, such as a node between closely-placed transistors, is facilitated.

    摘要翻译： 通过用于在半导体器件的后制造分析期间在半导体器件中的电路之间探测的方法和系统来增强对半导体器件的部分的访问。 根据本发明的示例性实施例，在具有在背侧相反的电路侧中的电路的半导体器件中形成细长的导电通孔探针。 通过首先从半导体器件去除衬底并在器件中的电路之间的目标节点上形成暴露区域来形成探针。 然后形成窄导体，用于与导体接合目标节点，并在电路之间延伸并进入后侧，并形成细长的导电通孔探针。 探头被访问并用于分析设备。 以这种方式，便于访问难以达到的目标节点，诸如紧密放置的晶体管之间的节点。

    Substrate removal as a function of SIMS analysis
    9.
    发明授权
    Substrate removal as a function of SIMS analysis 失效
    基板去除作为SIMS分析的功能

    公开(公告)号：US06281025B1

    公开(公告)日：2001-08-28

    申请号：US09409320

    申请日：1999-09-30

    申请人： Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis ,  Jeffrey D. Birdsley ,  Michael R. Bruce

    发明人： Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis ,  Jeffrey D. Birdsley ,  Michael R. Bruce

    IPC分类号： H01L2100

    CPC分类号： H01L22/26 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/15311

    摘要： Substrate removal for post-manufacturing analysis of a semiconductor device is enhanced via a method and system that utilizes ion beam etching, to etch the backside of a semiconductor chip, and utilizes SIMS as a detection technique to not only control removal of the substrate from the backside of the chip but also to determine the endpoint of the removal process. In an example embodiment there is described a method for removing substrate from the backside of a semiconductor chip as a function of detected concentration levels of a selected substrate material that is sputtered off of a region of the substrate.

    摘要翻译： 通过利用离子束蚀刻，蚀刻半导体芯片的背面的方法和系统来增强对半导体器件的后制造分析的衬底去除，并且利用SIMS作为检测技术，不仅可以控制从衬底的去除 芯片的背面还可以确定去除过程的终点。 在一个示例性实施例中，描述了从半导体芯片的背面去除衬底的方法，其作为从衬底区域溅射的所选择的衬底材料的检测浓度水平的函数。