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公开(公告)号：US07987229B1
公开(公告)日：2011-07-26
申请号：US11769744
申请日：2007-06-28
申请人： Jeffrey Kinne , John O'Shea , Michael Sgrosso , William F. Baxter, III , Christopher S. MacLellan
发明人： Jeffrey Kinne , John O'Shea , Michael Sgrosso , William F. Baxter, III , Christopher S. MacLellan
CPC分类号： G06F13/385 , G06F3/0658 , G06F13/28 , H04L67/1097
摘要： A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.
摘要翻译： 一种具有协议控制器的数据存储系统，用于在由存储处理器使用的PCIE格式和分组交换网使用的Rapid IO格式之间转换分组。 控制器包括用于传送原子操作（DSA）请求的PCIE端点，具有用于传递用户数据的多个数据管道的数据管段; 以及用于在多个存储处理器之间传递消息的消息引擎部分。 加速路径控制器在没有网络拥塞的情况下绕过DSA缓冲区。 馈送到PCIE端点的分组包括具有指示原子操作的代码的地址部分。 编码器将代码从PCIE格式转换为与SRIO格式相同的原子操作。 多个CPU中的每一个适于在执行第一DSA请求期间执行第二DSA请求。
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公开(公告)号：US07631128B1
公开(公告)日：2009-12-08
申请号：US11769747
申请日：2007-06-28
申请人： Michael Sgrosso , William F. Baxter, III , Jeffrey Kinne , Christopher S. MacLellan , John O'Shea
发明人： Michael Sgrosso , William F. Baxter, III , Jeffrey Kinne , Christopher S. MacLellan , John O'Shea
CPC分类号： G06F13/387 , G06F3/06 , G06F2213/0026 , H04L12/56
摘要： A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.
摘要翻译： 一种具有协议控制器的数据存储系统，用于在由存储处理器使用的PCIE格式和分组交换网使用的Rapid IO格式之间转换分组。 控制器包括用于传送原子操作（DSA）请求的PCIE端点，具有用于传递用户数据的多个数据管道的数据管段; 以及用于在多个存储处理器之间传递消息的消息引擎部分。 加速路径控制器在没有网络拥塞的情况下绕过DSA缓冲区。 馈送到PCIE端点的分组包括具有指示原子操作的代码的地址部分。 编码器将代码从PCIE格式转换为与SRIO格式相同的原子操作。 多个CPU中的每一个适于在执行第一DSA请求期间执行第二DSA请求。
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公开(公告)号：US08156220B1
公开(公告)日：2012-04-10
申请号：US11863530
申请日：2007-09-28
IPC分类号： G06F15/173 , G06F13/00 , G06F11/00
CPC分类号： G06F11/201 , G06F11/1443 , H04L67/1097
摘要： A method is provided for transmitting user data from a selected one of a plurality of data pipes. The method includes having a ring manager select one of the data pipes from a pool of the data pipes for transmission of the user data. The data is transmitted from the selected one of the data pipes at least one packet switching network. The data pipe detects whether there was an error in the transmission. If there an error detected, the data pipe generates an error interrupt for the ring manager. The ring manager detects the error interrupt and generates an error interrupt for a CPU. The ring manager removes the selected one of the data pipes from the pool of data pipes for a predetermined period of time while the ring manager continues to work on other tasks until the time has expired. During pipe retirement, the physical pipe removed from the pool of pipes is disabled and the router will then direct orphan packets to the error ring. When the time has expired, the ring manager returns the selected data pipe to the pool of available data pipes.
摘要翻译： 提供了一种用于从多个数据管道中选定的一个传送用户数据的方法。 该方法包括使环管理器从数据管道的池中选择一个数据管道，以传输用户数据。 数据从至少一个分组交换网络中的所选择的一个数据管道发送。 数据管道检测传输中是否有错误。 如果检测到错误，数据管道将为环管理器生成错误中断。 环管理器检测到错误中断，并为CPU产生错误中断。 环管理器在预定时间段内从数据管道池中移除所选择的一个数据管道，同时环管理器继续处理其他任务，直到时间到期。 在管道退役期间，从管道池中删除的物理管道被禁用，路由器然后将孤立的数据包引导到错误环。 当时间到期时，环管理器将所选数据管道返回到可用数据管道池。
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4.发明授权Data storage system having separate atomic operation/non-atomic operation paths 有权数据存储系统具有单独的原子操作/非原子操作路径公开(公告)号：US07707367B1
公开(公告)日：2010-04-27
申请号：US11769739
申请日：2007-06-28
CPC分类号： G06F13/4054
摘要： A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.
摘要翻译： 一种具有协议控制器的数据存储系统，用于在由存储处理器使用的PCIE格式和分组交换网使用的Rapid IO格式之间转换分组。 控制器包括用于传送原子操作（DSA）请求的PCIE端点，具有用于传递用户数据的多个数据管道的数据管段; 以及用于在多个存储处理器之间传递消息的消息引擎部分。 加速路径控制器在没有网络拥塞的情况下绕过DSA缓冲区。 馈送到PCIE端点的分组包括具有指示原子操作的代码的地址部分。 编码器将代码从PCIE格式转换为与SRIO格式相同的原子操作。 多个CPU中的每一个适于在执行第一DSA请求期间执行第二DSA请求。
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5.发明授权Data storage system having operation code in address portion for atomic operations 有权具有用于原子操作的地址部分中的操作码的数据存储系统公开(公告)号：US07979572B1
公开(公告)日：2011-07-12
申请号：US11769737
申请日：2007-06-28
IPC分类号： G06F15/16
CPC分类号： G06F13/387 , G06F2213/0026
摘要： A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.
摘要翻译： 一种具有协议控制器的数据存储系统，用于在由存储处理器使用的PCIE格式和分组交换网使用的Rapid IO格式之间转换分组。 控制器包括用于传送原子操作（DSA）请求的PCIE端点，具有用于传递用户数据的多个数据管道的数据管段; 以及用于在多个存储处理器之间传递消息的消息引擎部分。 加速路径控制器在没有网络拥塞的情况下绕过DSA缓冲区。 馈送到PCIE端点的分组包括具有指示原子操作的代码的地址部分。 编码器将代码从PCIE格式转换为与SRIO格式相同的原子操作。 多个CPU中的每一个适于在执行第一DSA请求期间执行第二DSA请求。
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6.发明授权Data storage system having acceleration path for congested packet switching network 有权数据存储系统具有拥塞分组交换网络的加速路径公开(公告)号：US07979588B1
公开(公告)日：2011-07-12
申请号：US11769740
申请日：2007-06-28
CPC分类号： G06F13/387 , G06F2213/0026
摘要： A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller passes a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.
摘要翻译： 一种具有协议控制器的数据存储系统，用于在由存储处理器使用的PCIE格式和分组交换网使用的快速IO格式之间转换分组。 控制器包括用于传送原子操作（DSA）请求的PCIE终点，具有用于传递用户数据的多个数据管道的数据管段; 以及用于在多个存储处理器之间传递消息的消息引擎部分。 加速路径控制器在没有网络拥塞的情况下通过DSA缓冲区。 馈送到PCIE端点的分组包括具有指示原子操作的代码的地址部分。 编码器将代码从PCIE格式转换为与SRIO格式相同的原子操作。 多个CPU中的每一个适于在执行第一DSA请求期间执行第二DSA请求。
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公开(公告)号：US08356124B1
公开(公告)日：2013-01-15
申请号：US10846386
申请日：2004-05-14
IPC分类号： G06F3/00 , G06F5/00 , G06F13/368 , G06F13/14 , H04L12/40
CPC分类号： G06F13/362
摘要： A data transfer system includes a PCI Express transaction layer having an input for serially receiving posted and non-posted request packets and completion packets; an application layer coupled to the PCI Express transaction layer for receiving posted and non-posted request packets and completion packets from the PCI Express transaction layer; a first transmission interface coupling the application layer to the PCI Express transaction layer; and a second transmission interface coupling the application layer to the PCI Express transaction layer. The PCI Express transaction layer transmits posted and non-posted request packets to the application layer over the first transmission interface and transmits completion packets to the application layer over the second transmission interface.
摘要翻译： 数据传输系统包括具有用于串行接收发布和未发布的请求分组和完成分组的输入的PCI Express事务层; 耦合到PCI Express事务层的应用层，用于从PCI Express事务层接收发布和未发布的请求分组和完成分组; 将应用层耦合到PCI Express事务层的第一传输接口; 以及将应用层耦合到PCI Express事务层的第二传输接口。 PCI Express事务层通过第一传输接口将发布和未发布的请求数据包发送到应用层，并通过第二个传输接口将完成数据包发送到应用层。
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8.发明授权Data storage system having CPUs adapted to perform a second atomic operation request prior to completion of a first atomic operation request 有权具有适于在完成第一原子操作请求之前执行第二原子操作请求的CPU的数据存储系统公开(公告)号：US07769928B1
公开(公告)日：2010-08-03
申请号：US11769743
申请日：2007-06-28
CPC分类号： G06F13/387 , G06F2213/0026
摘要： A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.
摘要翻译： 一种具有协议控制器的数据存储系统，用于在由存储处理器使用的PCIE格式和分组交换网使用的Rapid IO格式之间转换分组。 控制器包括用于传送原子操作（DSA）请求的PCIE终点，具有用于传递用户数据的多个数据管道的数据管段; 以及用于在多个存储处理器之间传递消息的消息引擎部分。 加速路径控制器在没有网络拥塞的情况下绕过DSA缓冲区。 馈送到PCIE端点的分组包括具有指示原子操作的代码的地址部分。 编码器将代码从PCIE格式转换为与SRIO格式相同的原子操作。 多个CPU中的每一个适于在执行第一DSA请求期间执行第二DSA请求。
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公开(公告)号：US07729239B1
公开(公告)日：2010-06-01
申请号：US11022998
申请日：2004-12-27
IPC分类号： G01R31/08 , G06F11/00 , G08C15/00 , H04J1/16 , H04J3/14 , H04L1/00 , H04L12/26 , H04L12/28 , H04L12/56 , H04L12/54
CPC分类号： H04L45/00 , H04L1/1874 , H04L45/302 , H04L45/40
摘要： An end point controller includes two of ingress/egress port pairs. A first one of the ingress/egress ports is adapted to send and receive one of a pair of types of information packets and a second one of the ingress/egress ports is adapted to send and receive the other one of the pair of types of information packets. A controller is coupled to the two port pairs for coupling one of ingress/egress ports to an input/output port selectively in accordance with the type of the information packet on the ingress/egress ports and the availability of the end point controller to a network. One of the egress ports is directly coupled to the output port to the network if the information packet is at such port and the end point controller has been granted access to the network while other information at the pair of egress ports is buffered prior to being coupled to the output. In like fashion, the input port from the network is directly coupled to one of the ingress ports if the information packet is of the type of information packet destined for such ingress port, said port being available to transmit the packet.
摘要翻译： 端点控制器包括入口/出口端口对中的两个。 入口/出口端口中的第一个适于发送和接收一对类型的信息分组中的一个，并且入口/出口端口中的第二个适于发送和接收一对类型的信息中的另一个 数据包 控制器耦合到两个端口对，以根据入口/出口端口上的信息分组的类型选择性地将输入/输出端口中的一个端口耦合到输入/输出端口，以及端点控制器到网络的可用性 。 如果信息分组处于这样的端口，则出口端口之一直接耦合到网络的输出端口，并且端点控制器已经被授权接入网络，而在对耦合端口的其他信息被耦合之前被缓冲 到输出。 如果信息分组是目的地为这样的入口端口的信息分组的类型，则来自网络的输入端口直接耦合到入口端口之一，所述端口可用于传送分组。
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公开(公告)号：US07124245B1
公开(公告)日：2006-10-17
申请号：US10675039
申请日：2003-09-30
申请人： John K. Walton , William F. Baxter, III , Kendell A. Chilton , Daniel Castel , Michael Bermingham , James M. Guyer
发明人： John K. Walton , William F. Baxter, III , Kendell A. Chilton , Daniel Castel , Michael Bermingham , James M. Guyer
IPC分类号： G06F12/00
CPC分类号： G06F12/0866
摘要： A system interface having: a plurality of front end directors adapted for coupling to a host computer/server; a plurality of back end directors adapted for coupling to a bank of disk drives; a data transfer section having cache memory; a cache memory manager; and, a message network. The cache memory is coupled to the plurality of front end and back end directors. The messaging network operates independently of the data transfer section and is coupled to the plurality of front end and back end. The front end and back end directors control data transfer between the host computer/server and the bank of disk drives in response to messages passing between the front end directors and the back end directors through the messaging network to facilitate data transfer between host computer/server and the bank of disk drives. The data passes through the cache memory in the data transfer section as such data passes between the host computer and the bank of disk drives. The system includes a cache memory manager having therein a memory for storing a map maintaining a relationship between data stored in the cache memory and data stored in the disk drives. The cache memory manager provides an interface between the host computer, the bank of disk drives and the cache memory for determining for the directors whether data to be read from the disk drives, or data to be written to the disk drives, resides in the cache memory. With such an arrangement, the cache memory in the data transfer section is not burdened with the task of transferring the director messaging but rather a messaging network is provided, operative independent of the data transfer section, for such messaging thereby increasing the operating bandwidth of the system interface. Further, the cache memory is no longer burdened with the task of evaluating whether data to be read from the disk drives, or data to be written to the disk drives, resides in the cache memory. The cache memory manager, plurality of front end directors, plurality of back end directors and cache memory are interconnected through a packet switching network.
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