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    Data Processing System, Processor and Method of Data Processing Having Improved Branch Target Address Cache
    1.
    发明申请
    Data Processing System, Processor and Method of Data Processing Having Improved Branch Target Address Cache 失效
    数据处理系统，具有改进的分支目标地址缓存的数据处理的处理器和方法

    公开(公告)号：US20080120496A1

    公开(公告)日：2008-05-22

    申请号：US11561002

    申请日：2006-11-17

    申请人： Jeffrey P. Bradford ,  Richard W. Doing ,  Richard J. Eickemeyer ,  Wael R. El-Essawy ,  Douglas R. Logan ,  Balaram Sinharoy ,  William E. Speight ,  Lixin Zhang

    发明人： Jeffrey P. Bradford ,  Richard W. Doing ,  Richard J. Eickemeyer ,  Wael R. El-Essawy ,  Douglas R. Logan ,  Balaram Sinharoy ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3806 ,  G06F9/30094 ,  G06F9/3013 ,  G06F9/3017 ,  G06F9/384 ,  G06F9/3844 ,  G06F9/3853

    摘要： A processor includes an execution unit and instruction sequencing logic that fetches instructions for execution. The instruction sequencing logic includes a branch target address cache having a branch target buffer containing a plurality of entries each associating at least a portion of a branch instruction address with a predicted branch target address. The branch target address cache accesses the branch target buffer using a branch instruction address to obtain a predicted branch target address for use as an instruction fetch address. The branch target address cache also includes a filter buffer that buffers one or more candidate branch target address predictions. The filter buffer associates a respective confidence indication indicative of predictive accuracy with each candidate branch target address prediction. The branch target address cache promotes candidate branch target address predictions from the filter buffer to the branch target buffer based upon their respective confidence indications.

    摘要翻译： 处理器包括一个执行单元和指令排序逻辑，它提取用于执行的指令。 指令排序逻辑包括具有分支目标缓冲器的分支目标地址高速缓存器，该分支目标缓冲器包含多个条目，每个条目将分支指令地址的至少一部分与预测的分支目标地址相关联。 分支目标地址高速缓存使用分支指令地址访问分支目标缓冲器，以获得用作指令获取地址的预测分支目标地址。 分支目标地址缓存还包括缓冲一个或多个候选分支目标地址预测的过滤器缓冲器。 滤波器缓冲器将表示预测精度的各个置信指示与每个候选分支目标地址预测相关联。 分支目标地址缓存基于它们各自的置信度指示来提高从过滤器缓冲器到分支目标缓冲器的候选分支目标地址预测。

    Just-In-Time Prefetching
    5.
    发明申请
    Just-In-Time Prefetching 失效
    即时预取

    公开(公告)号：US20070283101A1

    公开(公告)日：2007-12-06

    申请号：US11422459

    申请日：2006-06-06

    申请人： Wael R. El-Essawy ,  Ramakrishnan Rajamony ,  Hazim Shafi ,  William E. Speight ,  Lixin Zhang

    发明人： Wael R. El-Essawy ,  Ramakrishnan Rajamony ,  Hazim Shafi ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0862

    摘要： A method and an apparatus for performing just-in-time data prefetching within a data processing system comprising a processor, a cache or prefetch buffer, and at least one memory storage device. The apparatus comprises a prefetch engine having means for issuing a data prefetch request for prefetching a data cache line from the memory storage device for utilization by the processor. The apparatus further comprises logic/utility for dynamically adjusting a prefetch distance between issuance by the prefetch engine of the data prefetch request and issuance by the processor of a demand (load request) targeting the data/cache line being returned by the data prefetch request, so that a next data prefetch request for a subsequent cache line completes the return of the data/cache line at effectively the same time that a demand for that subsequent data/cache line is issued by the processor.

    摘要翻译： 一种用于在包括处理器，高速缓存或预取缓冲器的数据处理系统中执行即时数据预取的方法和装置，以及至少一个存储器存储装置。 该装置包括预取引擎，具有用于发出数据预取请求的装置，用于从存储器存储装置预取数据高速缓存行以供处理器利用。 该装置还包括逻辑/实用程序，用于动态地调整数据预取请求的预取引擎的发布之间的预取距离，并且由处理器发出针对由数据预取请求返回的数据/高速缓存线的需求（加载请求） 使得对于后续高速缓存行的下一个数据预取请求在处理器发出对后续数据/高速缓存行的请求的同时有效地完成数据/高速缓存行的返回。

    Efficient multiple-table reference prediction mechanism
    6.
    发明授权
    Efficient multiple-table reference prediction mechanism 失效
    高效多表参考预测机制

    公开(公告)号：US07657729B2

    公开(公告)日：2010-02-02

    申请号：US11457178

    申请日：2006-07-13

    申请人： Wael R. El-Essawy ,  Ramakrishnan Rajamony ,  Hazim Shafi ,  William E. Speight ,  Lixin Zhang

    发明人： Wael R. El-Essawy ,  Ramakrishnan Rajamony ,  Hazim Shafi ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F9/00

    CPC分类号： G06F12/0862 ,  G06F9/3455 ,  G06F9/383 ,  G06F9/3832 ,  G06F12/0897 ,  G06F2212/6026

    摘要： A method and an apparatus for enabling a prefetch engine to detect and support hardware prefetching with different streams in received accesses. Multiple (simple) history tables are provided within (or associated with) the prefetch engine. Each of the multiple tables is utilized to detect different access patterns. The tables are indexed by different parts of the address and are accessed in a preset order to reduce the interference between different patterns. When an address does not fit the patterns of a first table, the address is passed to the next table to be checked for a match of different patterns. In this manner, different patterns may be detected at different tables within a single prefetch engine.

    摘要翻译： 一种用于使预取引擎能够在接收的访问中检测和支持不同流的硬件预取的方法和装置。 在预取引擎（或与其相关联）中提供了多个（简单）历史表。 多个表中的每一个用于检测不同的访问模式。 这些表由地址的不同部分索引，并以预设顺序访问，以减少不同模式之间的干扰。 当地址不符合第一个表的模式时，该地址将传递给下一个表，以便检查不同模式的匹配。 以这种方式，可以在单个预取引擎内的不同表处检测不同的模式。

    Dynamically adjusting a pre-fetch distance to enable just-in-time prefetching within a processing system
    8.
    发明授权
    Dynamically adjusting a pre-fetch distance to enable just-in-time prefetching within a processing system 失效
    动态调整预取距离，以便在处理系统中实现即时预取

    公开(公告)号：US07487297B2

    公开(公告)日：2009-02-03

    申请号：US11422459

    申请日：2006-06-06

    申请人： Wael R. El-Essawy ,  Ramakrishnan Rajamony ,  Hazim Shafi ,  William E. Speight ,  Lixin Zhang

    发明人： Wael R. El-Essawy ,  Ramakrishnan Rajamony ,  Hazim Shafi ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F13/00

    CPC分类号： G06F12/0862

    摘要： A method and an apparatus for performing just-in-time data prefetching within a data processing system comprising a processor, a cache or prefetch buffer, and at least one memory storage device. The apparatus comprises a prefetch engine having means for issuing a data prefetch request for prefetching a data cache line from the memory storage device for utilization by the processor. The apparatus further comprises logic/utility for dynamically adjusting a prefetch distance between issuance by the prefetch engine of the data prefetch request and issuance by the processor of a demand (load request) targeting the data/cache line being returned by the data prefetch request, so that a next data prefetch request for a subsequent cache line completes the return of the data/cache line at effectively the same time that a demand for that subsequent data/cache line is issued by the processor.

    摘要翻译： 一种用于在包括处理器，高速缓存或预取缓冲器的数据处理系统中执行即时数据预取的方法和装置，以及至少一个存储器存储装置。 该装置包括预取引擎，具有用于发出数据预取请求的装置，用于从存储器存储装置预取数据高速缓存行以供处理器利用。 该装置还包括逻辑/实用程序，用于动态地调整数据预取请求的预取引擎的发布之间的预取距离，并且由处理器发出针对由数据预取请求返回的数据/高速缓存线的需求（加载请求） 使得对于后续高速缓存行的下一个数据预取请求在处理器发出对后续数据/高速缓存行的请求的同时有效地完成数据/高速缓存行的返回。

    Efficient Multiple-Table Reference Prediction Mechanism
    9.
    发明申请
    Efficient Multiple-Table Reference Prediction Mechanism 失效
    高效多表参考预测机制

    公开(公告)号：US20080016330A1

    公开(公告)日：2008-01-17

    申请号：US11457178

    申请日：2006-07-13

    申请人： Wael R. El-Essawy ,  Ramakrishnan Rajamony ,  Hazim Shafi ,  William E. Speight ,  Lixin Zhang

    发明人： Wael R. El-Essawy ,  Ramakrishnan Rajamony ,  Hazim Shafi ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F9/44

    CPC分类号： G06F12/0862 ,  G06F9/3455 ,  G06F9/383 ,  G06F9/3832 ,  G06F12/0897 ,  G06F2212/6026

    摘要： A method and an apparatus for enabling a prefetch engine to detect and support hardware prefetching with different streams in received accesses. Multiple (simple) history tables are provided within (or associated with) the prefetch engine. Each of the multiple tables is utilized to detect different access patterns. The tables are indexed by different parts of the address and are accessed in a preset order to reduce the interference between different patterns. When an address does not fit the patterns of a first table, the address is passed to the next table to be checked for a match of different patterns. In this manner, different patterns may be detected at different tables within a single prefetch engine.

    摘要翻译： 一种用于使预取引擎能够在接收的访问中检测和支持不同流的硬件预取的方法和装置。 在预取引擎（或与其相关联）中提供了多个（简单）历史表。 多个表中的每一个用于检测不同的访问模式。 这些表由地址的不同部分索引，并以预设顺序访问，以减少不同模式之间的干扰。 当地址不符合第一个表的模式时，该地址将传递给下一个表，以便检查不同模式的匹配。 以这种方式，可以在单个预取引擎内的不同表处检测不同的模式。

    Varying an amount of data retrieved from memory based upon an instruction hint
    10.
    发明授权
    Varying an amount of data retrieved from memory based upon an instruction hint 失效
    根据指令提示改变从存储器检索的数据量

    公开(公告)号：US08266381B2

    公开(公告)日：2012-09-11

    申请号：US12024170

    申请日：2008-02-01

    申请人： Ravi K. Arimilli ,  Gheorghe C. Cascaval ,  Balaram Sinharoy ,  William E. Speight ,  Lixin Zhang

    发明人： Ravi K. Arimilli ,  Gheorghe C. Cascaval ,  Balaram Sinharoy ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0862 ,  G06F12/0822 ,  G06F2212/507 ,  G06F2212/6028

    摘要： In at least one embodiment, a processor detects during execution of program code whether a load instruction within the program code is associated with a hint. In response to detecting that the load instruction is not associated with a hint, the processor retrieves a full cache line of data from the memory hierarchy into the processor in response to the load instruction. In response to detecting that the load instruction is associated with a hint, a processor retrieves a partial cache line of data into the processor from the memory hierarchy in response to the load instruction.

    摘要翻译： 在至少一个实施例中，处理器在执行程序代码期间检测程序代码内的加载指令是否与提示相关联。 响应于检测到加载指令不与提示相关联，处理器响应于加载指令从存储器层次结构检索完整的高速缓存行数据到处理器。 响应于检测到加载指令与提示相关联，处理器响应于加载指令从存储器层次结构检索数据的部分高速缓存行到处理器中。