公开(公告)号：US20100090304A1

公开(公告)日：2010-04-15

申请号：US12626296

申请日：2009-11-25

申请人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Shou-Gwo Wuu

发明人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Shou-Gwo Wuu

IPC分类号： H01L31/0232 ,  H01L31/18 ,  H01L21/60

CPC分类号： H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/12 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/12043 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

摘要： The present disclosure provides a method of making an integrated circuit (IC). The method includes forming an electric device on a front side of a substrate; forming a top metal pad on the front side of the substrate, the top metal pad being coupled to the electric device; forming a passivation layer on the front side of the substrate, the top metal pad being embedded in the passivation layer; forming an opening in the passivation layer, exposing the top metal pad; forming a deep trench in the substrate; filling a conductive material in the deep trench and the opening, resulting in a though-wafer via (TWV) feature in the deep trench and a pad-TWV feature in the opening, where the top metal pad being connected to the TWV feature through the pad-TWV feature; and applying a polishing process to remove excessive conductive material, forming a substantially planar surface.

摘要翻译： 本公开提供了制造集成电路（IC）的方法。 该方法包括在基板的正面上形成电子装置; 在所述基板的前侧形成顶部金属焊盘，所述顶部金属焊盘联接到所述电气装置; 在所述基板的正面上形成钝化层，所述顶部金属焊盘嵌入所述钝化层中; 在钝化层中形成开口，暴露顶部金属垫; 在衬底中形成深沟槽; 在深沟槽和开口中填充导电材料，导致深沟槽中的贯穿晶片通孔（TWV）特征和开口中的焊盘TWV特征，其中顶部金属焊盘通过该沟槽连接到TWV特征 pad-TWV功能; 以及施加抛光工艺以去除过量的导电材料，形成基本平坦的表面。

公开(公告)号：US08278152B2

公开(公告)日：2012-10-02

申请号：US12626296

申请日：2009-11-25

申请人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Shou-Gwo Wuu

发明人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Shou-Gwo Wuu

IPC分类号： H01L21/44

CPC分类号： H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/12 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/12043 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

摘要： The present disclosure provides a method of making an integrated circuit (IC). The method includes forming an electric device on a front side of a substrate; forming a top metal pad on the front side of the substrate, the top metal pad being coupled to the electric device; forming a passivation layer on the front side of the substrate, the top metal pad being embedded in the passivation layer; forming an opening in the passivation layer, exposing the top metal pad; forming a deep trench in the substrate; filling a conductive material in the deep trench and the opening, resulting in a though-wafer via (TWV) feature in the deep trench and a pad-TWV feature in the opening, where the top metal pad being connected to the TWV feature through the pad-TWV feature; and applying a polishing process to remove excessive conductive material, forming a substantially planar surface.

摘要翻译： 本公开提供了制造集成电路（IC）的方法。 该方法包括在基板的正面上形成电子装置; 在所述基板的前侧形成顶部金属焊盘，所述顶部金属焊盘联接到所述电气装置; 在所述基板的正面上形成钝化层，所述顶部金属焊盘嵌入所述钝化层中; 在钝化层中形成开口，暴露顶部金属垫; 在衬底中形成深沟槽; 在深沟槽和开口中填充导电材料，导致深沟槽中的贯穿晶片通孔（TWV）特征和开口中的焊盘TWV特征，其中顶部金属焊盘通过该沟槽连接到TWV特征 pad-TWV功能; 以及施加抛光工艺以去除过量的导电材料，形成基本平坦的表面。

公开(公告)号：US20090146325A1

公开(公告)日：2009-06-11

申请号：US11951916

申请日：2007-12-06

申请人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu

发明人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu

IPC分类号： H01L23/544 ,  H01L21/46

CPC分类号： H01L23/544 ,  H01L21/71 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An apparatus and manufacturing method thereof, wherein an integrated circuit is located in a first region of a substrate having first and second opposing major surfaces, and wherein an alignment mark is located in a second region of the substrate and extends through the substrate between the first and second surfaces. The alignment mark may protrude from the first and/or second surfaces, and/or may comprise a plurality of substantially similar alignment marks. The second region may interpose the first region and a perimeter of the substrate. The second region may comprise a scribe region.

摘要翻译： 一种装置及其制造方法，其中集成电路位于具有第一和第二相对主表面的基板的第一区域中，并且其中对准标记位于所述基板的第二区域中，并且延伸穿过所述基板在所述第一 和第二表面。 对准标记可以从第一和/或第二表面突出，和/或可以包括多个基本相似的对准标记。 第二区域可以插入衬底的第一区域和周边。 第二区域可以包括划线区域。

公开(公告)号：US08558351B2

公开(公告)日：2013-10-15

申请号：US13550140

申请日：2012-07-16

申请人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu

发明人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L21/71 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Provided is an apparatus that includes an integrated circuit located in a first region of a substrate having first and second opposing major surfaces and an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces.

摘要翻译： 提供了一种装置，其包括位于具有第一和第二相对主表面的基板的第一区域中的集成电路和位于基板的第二区域中并在第一和第二表面之间延伸穿过基板的对准标记。

公开(公告)号：US20120280351A1

公开(公告)日：2012-11-08

申请号：US13550140

申请日：2012-07-16

申请人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu

发明人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu

IPC分类号： H01L23/544 ,  H01L27/146

CPC分类号： H01L23/544 ,  H01L21/71 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Provided is an apparatus that includes an integrated circuit located in a first region of a substrate having first and second opposing major surfaces and an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces.

摘要翻译： 提供了一种装置，其包括位于具有第一和第二相对主表面的基板的第一区域中的集成电路和位于基板的第二区域中并在第一和第二表面之间延伸穿过基板的对准标记。

公开(公告)号：US08227899B2

公开(公告)日：2012-07-24

申请号：US12553586

申请日：2009-09-03

申请人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu

发明人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L21/71 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Provided is an apparatus that includes an integrated circuit located in a first region of a substrate having first and second opposing major surfaces and an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces.

摘要翻译： 提供了一种装置，其包括位于具有第一和第二相对主表面的基板的第一区域中的集成电路和位于基板的第二区域中并在第一和第二表面之间延伸穿过基板的对准标记。

公开(公告)号：US20090189233A1

公开(公告)日：2009-07-30

申请号：US12020149

申请日：2008-01-25

申请人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Chi-Hsin Lo ,  Feng-Jia Shiu ,  Chung-Yi Yu

发明人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Chi-Hsin Lo ,  Feng-Jia Shiu ,  Chung-Yi Yu

IPC分类号： H01L31/0232 ,  H01L31/18

CPC分类号： H01L27/14625 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14685

摘要： An optical image sensor is fabricated by forming a pixel array and a peripheral region surrounding the pixel array on a semiconductor substrate, the peripheral region containing peripheral circuitry. An inter-level-dielectric layer is formed over the substrate and a plurality of interconnect wiring layers are formed over the inter-level-dielectric layer. Each interconnect wiring layer includes interconnecting metal features and a layer of inter-level-dielectric material covering the interconnecting metal features. The plurality of interconnect wiring layers are provided in a manner that there are N levels of wiring layers in the peripheral region and 1 to (N−1) levels of wiring layers over the pixel array. An etch-stop layer is formed over the top-most level interconnecting metal features in the peripheral region.

摘要翻译： 通过在半导体衬底上形成围绕像素阵列的像素阵列和外围区域来制造光学图像传感器，该外围区域包含外围电路。 层间电介质层形成在衬底之上，并且在层间电介质层之上形成多个互连布线层。 每个互连布线层包括互连金属特征和覆盖互连金属特征的层间电介质材料层。 多个互连布线层的设置方式是在像素阵列的周边区域中有N层布线层和布线层的1层（N-1）层。 在外围区域中最顶层的互连金属特征上形成蚀刻停止层。

公开(公告)号：US07588993B2

公开(公告)日：2009-09-15

申请号：US11951916

申请日：2007-12-06

申请人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu

发明人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu

IPC分类号： H01L21/76

CPC分类号： H01L23/544 ,  H01L21/71 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An apparatus and manufacturing method thereof, wherein an integrated circuit is located in a first region of a substrate having first and second opposing major surfaces, and wherein an alignment mark is located in a second region of the substrate and extends through the substrate between the first and second surfaces. The alignment mark may protrude from the first and/or second surfaces, and/or may comprise a plurality of substantially similar alignment marks. The second region may interpose the first region and a perimeter of the substrate. The second region may comprise a scribe region.

摘要翻译： 一种装置及其制造方法，其中集成电路位于具有第一和第二相对主表面的基板的第一区域中，并且其中对准标记位于所述基板的第二区域中，并且延伸穿过所述基板在所述第一 和第二表面。 对准标记可以从第一和/或第二表面突出，和/或可以包括多个基本相似的对准标记。 第二区域可以插入衬底的第一区域和周边。 第二区域可以包括划线区域。

公开(公告)号：US20090321888A1

公开(公告)日：2009-12-31

申请号：US12553586

申请日：2009-09-03

申请人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu

发明人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L21/71 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Provided is an apparatus that includes an integrated circuit located in a first region of a substrate having first and second opposing major surfaces and an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces.

摘要翻译： 提供了一种装置，其包括位于具有第一和第二相对主表面的基板的第一区域中的集成电路和位于基板的第二区域中并在第一和第二表面之间延伸穿过基板的对准标记。

公开(公告)号：US10090349B2

公开(公告)日：2018-10-02

申请号：US13571099

申请日：2012-08-09

申请人： Meng-Hsun Wan ,  Szu-Ying Chen ,  Dun-Nian Yaung ,  Jen-Cheng Liu

发明人： Meng-Hsun Wan ,  Szu-Ying Chen ,  Dun-Nian Yaung ,  Jen-Cheng Liu

IPC分类号： H01L27/146

摘要： A device includes an image sensor chip having an image sensor therein. A read-out chip is underlying and bonded to the image sensor chip, wherein the read-out chip includes a logic device selected from the group consisting essentially of a reset transistor, a source follower, a row selector, and combinations thereof therein. The logic device and the image sensor are electrically coupled to each other, and are parts of a same pixel unit. A peripheral circuit chip is underlying and bonded to the read-out chip, wherein the peripheral circuit chip includes a logic circuit.