公开(公告)号：US06978191B2

公开(公告)日：2005-12-20

申请号：US10656757

申请日：2003-09-06

Applicant: Yo-Nien Lin ,  Kuan-Luan Cheng ,  Kun-Pi Cheng ,  Hsin-Yuan Chen

Inventor： Yo-Nien Lin ,  Kuan-Luan Cheng ,  Kun-Pi Cheng ,  Hsin-Yuan Chen

IPC: G03F7/20 ,  G06F7/00 ,  G06F19/00 ,  H01L21/00

CPC classification number: H01L21/67253 ,  G03F7/70508 ,  G03F7/70633

Abstract: A method for fabricating a microelectronic product and a system for fabricating the microelectronic product each employ an in-line automatic photolithographic processing and overlay registration measurement for a pair of pilot lots of a new product order, prior to in-line automatic processing of an additional new product order lot within a photolithographic process tool. The method and the system provide for efficient production of new product order lots, absent need for an independent pilot lot qualification method or system.

Abstract translation: 用于制造微电子产品的方法和用于制造微电子产品的系统各自在一个新的产品订单的一对先导批次之前采用在线自动光刻处理和重叠配准测量，在一个额外的在线自动处理之前 新产品订单在光刻工艺工具中。 该方法和系统提供了新产品订单批量的高效生产，不需要独立的试点批次认证方法或系统。

公开(公告)号：US06507394B1

公开(公告)日：2003-01-14

申请号：US09449884

申请日：1999-11-30

Applicant: Kun-Pi Cheng ,  I-Chung Chang

Inventor： Kun-Pi Cheng ,  I-Chung Chang

IPC: G01N2100

CPC classification number: G01N21/9501

Abstract: An optical inspection system for detecting defects on the surface of a semiconductor wafer includes two light sources and two light receivers mounted as a common assembly which is rotated such that two curtains of light and corresponding linear photosensor arrays circularly scan the wafer surface. The reflected light is analyzed to determine the presence of surface defects. Marks applied to the wafer surface provide amplitude and timing references used to adjust and synchronize the analyzed signals.

Abstract translation: 用于检测半导体晶片表面上的缺陷的光学检查系统包括两个光源和两个光接收器，其安装为共同组件，其被旋转使得两个窗帘和相应的线性光电传感器阵列循环扫描晶片表面。 分析反射光以确定表面缺陷的存在。 施加到晶片表面的标记提供用于调整和同步分析的信号的幅度和定时参考。

公开(公告)号：US5902707A

公开(公告)日：1999-05-11

申请号：US118035

申请日：1998-07-17

Applicant: Tsu-Yu Chu ,  Jui-Yu Chang ,  Kun-Pi Cheng

Inventor： Tsu-Yu Chu ,  Jui-Yu Chang ,  Kun-Pi Cheng

IPC: G03F1/00 ,  G03F7/00 ,  G03F9/00

CPC classification number: G03F9/70 ,  G03F1/42 ,  G03F7/0035 ,  Y10S148/102 ,  Y10S438/975

Abstract: A mask, which does not require additional reticles, and a method of using the mask for recovering alignment marks in a wafer after an inter-level dielectric layer has been planarized and a second layer of metal has been deposited on the planarized inter-level dielectric layer are described. An alignment mark protection pattern and a clearout window pattern are sub-divided so they can be formed from a first and a second mask element. These mask elements can be formed in the peripheral region of the reticle used to pattern the device region of the wafer. The mask elements are used to expose the alignment mark protection pattern in a first layer of photoresist and the clearout window pattern in a second layer of photoresist.

Abstract translation: 不需要额外的掩模版的掩模，以及在层间电介质层已被平坦化之后使用掩模来恢复晶片中的对准标记的方法，并且第二层金属已沉积在平坦化的层间电介质上 描述层。 对准标记保护图案和清晰窗口图案被细分，使得它们可以由第一和第二掩模元件形成。 这些掩模元件可以形成在用于对晶片的器件区域进行图案化的掩模版的周边区域中。 掩模元件用于在光致抗蚀剂的第一层中曝光对准标记保护图案，并在第二层光致抗蚀剂中露出清漆窗口图案。

公开(公告)号：US07031794B2

公开(公告)日：2006-04-18

申请号：US10672394

申请日：2003-09-26

Applicant: Kun-Pi Cheng ,  Hsin-Yuan Chen ,  Yo-Nien Lin ,  Feng-Cheng Chung

Inventor： Kun-Pi Cheng ,  Hsin-Yuan Chen ,  Yo-Nien Lin ,  Feng-Cheng Chung

IPC: G06F19/00

CPC classification number: G03F7/70633 ,  G03F7/70525

Abstract: An automatic method to maintain and correct overlay in the fabrication of integrated circuits is described. An overlay control table is automatically generated for lots run through a process tool. An overlay correction is calculated from the overlay control table and sent to the process tool for real-time or manual overlay correction.

Abstract translation: 描述了在集成电路的制造中维护和校正覆盖的自动方法。 自动生成覆盖控制表，用于批处理工具。 从覆盖控制表计算覆盖校正，并发送到过程工具进行实时或手动叠加校正。

公开(公告)号：US06396567B1

公开(公告)日：2002-05-28

申请号：US09324129

申请日：1999-06-02

Applicant: Tsu-Yu Chu ,  I-Chung Chang ,  Kun-Pi Cheng

Inventor： Tsu-Yu Chu ,  I-Chung Chang ,  Kun-Pi Cheng

IPC: G03B2772

CPC classification number: G03F7/70058 ,  G03F7/70066 ,  G03F7/70075 ,  G03F7/70191 ,  G03F7/70358 ,  G03F7/70558

Abstract: The two dimensional intensity profile of radiation applied to a semiconductor wafer during photolithography is controlled by passing the radiation beam through an attenuating member before the beam is imaged by a mask onto the wafer. The attenuating member is preferably ring shaped and is formed of a semi-transparent material such as Mo Bi Si O4, or a material that is partially reflective of the radiation.

Abstract translation: 在光刻期间施加到半导体晶片的辐射的二维强度分布通过在通过掩模将光束成像到晶片之前使辐射束通过衰减部件来控制。 衰减构件优选为环形，并且由诸如Mo Bi Si O 4的半透明材料或部分反射辐射的材料形成。

公开(公告)号：US06357131B1

公开(公告)日：2002-03-19

申请号：US09467113

申请日：1999-12-20

Applicant: Kun Pi Cheng ,  I-Chung Chang

Inventor： Kun Pi Cheng ,  I-Chung Chang

IPC: G01B1126

CPC classification number: G03F7/70633 ,  H01L2223/54453 ,  H01L2223/54493

Abstract: A method of overlaying two images and from this overlay observe and measure the accuracy of the alignment of the wafer. Wafer misalignment can be readily corrected based on the results of these observations. Alignment marks are provided on the surface of the wafer that is being validated for accuracy of alignment. The position of this mark relative to a pattern provided on the surface of a control wafer is measured and forms an indication of the alignment of the wafer.

Abstract translation: 覆盖两个图像并从该覆盖物的方法观察并测量晶片对准的精度。 基于这些观察结果可以很容易地校正晶圆偏移。 对准标记提供在正在验证的晶圆表面上以进行对准精度。 该标记相对于设置在控制晶片的表面上的图案的位置被测量并且形成晶片对准的指示。

公开(公告)号：US5843600A

公开(公告)日：1998-12-01

申请号：US901168

申请日：1997-07-28

Applicant: Tsu-Yu Chu ,  Jui-Yu Chang ,  Kun-Pi Cheng

Inventor： Tsu-Yu Chu ,  Jui-Yu Chang ,  Kun-Pi Cheng

IPC: G03F1/00 ,  G03F7/00 ,  G03F9/00

CPC classification number: G03F9/70 ,  G03F1/42 ,  G03F7/0035 ,  Y10S148/102 ,  Y10S438/975

Abstract: A mask, which does not require additional reticles, and a method of using the mask for recovering alignment marks in a wafer after an inter-level dielectric layer has been planarized and a second layer of metal has been deposited on the planarized inter-level dielectric layer are described. An alignment mark protection pattern and a clearout window pattern are sub-divided so they can be formed from a first and a second mask element. These mask elements can be formed in the peripheral region of the reticle used to pattern the device region of the wafer. The mask elements are used to expose the alignment mark protection pattern in a first layer of photoresist and the clearout window pattern in a second layer of photoresist.

Abstract translation: 不需要额外的掩模版的掩模，以及在层间电介质层已被平坦化之后使用掩模来恢复晶片中的对准标记的方法，并且第二层金属已沉积在平坦化的层间电介质上 描述层。 对准标记保护图案和清晰窗口图案被细分，使得它们可以由第一和第二掩模元件形成。 这些掩模元件可以形成在用于对晶片的器件区域进行图案化的掩模版的周边区域中。 掩模元件用于在光致抗蚀剂的第一层中曝光对准标记保护图案，并在第二层光致抗蚀剂中露出清漆窗口图案。

公开(公告)号：US20050055122A1

公开(公告)日：2005-03-10

申请号：US10656757

申请日：2003-09-06

Applicant: To-Nien Lin ,  Kuan-Luan Cheng ,  Kun-Pi Cheng ,  Hsin-Yuan Chen

Inventor： To-Nien Lin ,  Kuan-Luan Cheng ,  Kun-Pi Cheng ,  Hsin-Yuan Chen

IPC: G03F7/20 ,  G06F7/00 ,  G06F19/00 ,  H01L21/00

CPC classification number: H01L21/67253 ,  G03F7/70508 ,  G03F7/70633

Abstract: A method for fabricating a microelectronic product and a system for fabricating the microelectronic product each employ an in-line automatic photolithographic processing and overlay registration measurement for a pair of pilot lots of a new product order, prior to in-line automatic processing of an additional new product order lot within a photolithographic process tool. The method and the system provide for efficient production of new product order lots, absent need for an independent pilot lot qualification method or system.

公开(公告)号：US06735485B1

公开(公告)日：2004-05-11

申请号：US10290925

申请日：2002-11-08

Applicant: Wen-Hung Wu ,  Kun-Pi Cheng

Inventor： Wen-Hung Wu ,  Kun-Pi Cheng

IPC: G05B1900

CPC classification number: G03F7/70633 ,  G03F7/70491 ,  G05B2219/50151

Abstract: A method for determining an overlay registration correction for a new product lot of a microelectronic product type with respect to a specific alignment tool within a foundry facility first provides for determining: (1) a first average historic overlay registration correction for historic product lots of the new product lot type with respect to the specific alignment tool; and (2) a second average historic overlay registration correction with respect to product lots of any product type with respect to the specific alignment tool. The overlay registration correction is determined as the sum of: (1) an overlay registration correction for an immediately preceding layer within the new product lot, if present; (2) a factor derived from the first average historic overlay registration correction; and (3) a factor derived from the second average historic overlay registration correction.

Abstract translation: 用于确定关于铸造设备中的特定对准工具的微电子产品类型的新产品批次的重叠注册校正的方法首先确定：（1）针对历史产品批次的第一平均历史重叠注册校正 新产品批次类型相对于具体的对齐工具; 和（2）相对于特定对准工具的任何产品类型的产品批次的第二平均历史重叠登记修正。 确定覆盖登记修正为：（1）如果存在新产品批次中的紧邻前一层的叠加登记修正; （2）从第一次平均历史重叠登记纠正得出的因子; 和（3）来自第二平均历史重叠登记修正的因子。

公开(公告)号：US20050158966A1

公开(公告)日：2005-07-21

申请号：US10761657

申请日：2004-01-20

Applicant: Chin-Kun Fang ,  Kun-Pi Cheng ,  Wei-Jen Wu ,  Ching-Jiunn Huang ,  Chung-Jen Chen

Inventor： Chin-Kun Fang ,  Kun-Pi Cheng ,  Wei-Jen Wu ,  Ching-Jiunn Huang ,  Chung-Jen Chen

IPC: H01L21/76 ,  H01L21/762 ,  H01L23/544

CPC classification number: H01L21/76229 ,  H01L23/544 ,  H01L2223/54493 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: A semiconductor process wafer having substantially co-planar active areas and a laser marked area in an adjacent inactive area and method for forming the same to eliminate a step height and improve a subsequent patterning process over the active areas wherein an inactive area trench is formed overlying the laser marked area in parallel with formation of STI trenches in the active area whereby the active areas and the inactive area are formed substantially co-planar without a step height.

Abstract translation: 具有相邻非活性区域中基本上共平面的有源区和激光标记区的半导体工艺晶片及其形成方法以消除台阶高度并改善在有源区上的后续图案化工艺，其中形成无效区沟槽 激光标记区域与有源区域中的STI沟槽的形成平行，由此有源区域和非活性区域形成为基本上没有台阶高度共面。