公开(公告)号：US06465897B1

公开(公告)日：2002-10-15

申请号：US09472923

申请日：1999-12-27

申请人： Tsu Shih ,  Jui-Yu Chang

发明人： Tsu Shih ,  Jui-Yu Chang

IPC分类号： H01L2348

CPC分类号： G03F9/708 ,  G03F9/7084 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming alignment marks are disclosed for performing photoalignment after chemical-mechanical polishing (CMP). A trench is first formed in a silicon substrate and then alignment marks are formed at the bottom of the trench. The aspect ratio of the trench is selected to be so low that the dishing of the CMP pad can be prevented from reaching into the trench to damage the alignment marks therein. A trench structure is also provided whereby the alignment marks can be protected from the abrasive action of the CMP. Steps subsequent to the CMP can therefore proceed unimpeded with the presence of undamaged alignment marks.

摘要翻译： 公开了用于在化学机械抛光（CMP）之后进行光对准的形成对准标记的方法。 首先在硅衬底中形成沟槽，然后在沟槽的底部形成对准标记。 选择沟槽的纵横比非常低以致可以防止CMP焊盘的凹陷进入沟槽以损坏其中的对准标记。 还提供沟槽结构，由此可以保护对准标记免受CMP的研磨作用。 因此，CMP之后的步骤可以不受阻碍地对准标记的存在而不受阻碍地进行。

公开(公告)号：US5972798A

公开(公告)日：1999-10-26

申请号：US86775

申请日：1998-05-29

申请人： Syun-Ming Jang ,  Jui-Yu Chang ,  Chen-Hua Yu ,  Chung-Long Chang ,  Tsu Shih ,  Jeng-Horng Chen

发明人： Syun-Ming Jang ,  Jui-Yu Chang ,  Chen-Hua Yu ,  Chung-Long Chang ,  Tsu Shih ,  Jeng-Horng Chen

IPC分类号： H01L23/544 ,  H01L21/00

CPC分类号： H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2924/0002 ,  Y10S438/942

摘要： Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modem high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.

摘要翻译： 描述了在将半导体晶片加工成集成电路器件期间形成拓扑特征的新颖方法。 本发明对于用于形成先进的多级超大规模集成电路的那些工艺是最有用的，其中使用诸如化学机械抛光的全局平面化技术。 本发明适用于用于形成调制解调器高密度多电平集成电路的所有方法，而不受所形成的层数或使用的材料的影响。 在本发明中，衬底是半导体晶片或其一部分，并且是所述工艺改变并形成层的材料。

公开(公告)号：US06444371B1

公开(公告)日：2002-09-03

申请号：US09377541

申请日：1999-08-19

申请人： Syun-Ming Jang ,  Jui-Yu Chang ,  Chen-Hua Yu ,  Chung-Long Chang ,  Tsu Shih ,  Jeng-Horng Chen

发明人： Syun-Ming Jang ,  Jui-Yu Chang ,  Chen-Hua Yu ,  Chung-Long Chang ,  Tsu Shih ,  Jeng-Horng Chen

IPC分类号： G03F900

CPC分类号： H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2924/0002 ,  Y10S438/942 ,  H01L2924/00

摘要： Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modern high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.

摘要翻译： 描述了在将半导体晶片加工成集成电路器件期间形成拓扑特征的新颖方法。 本发明对于用于形成先进的多级超大规模集成电路的那些工艺是最有用的，其中使用诸如化学机械抛光的全局平面化技术。 本发明适用于用于形成现代高密度，多级集成电路的所有方法，并且不受所形成的层数或使用的材料的影响。 在本发明中，衬底是半导体晶片或其一部分，并且是所述工艺改变并形成层的材料。

公开(公告)号：US6020249A

公开(公告)日：2000-02-01

申请号：US891088

申请日：1997-07-10

申请人： Tsu Shih ,  Jui-Yu Chang ,  Syun-Ming Jang ,  Chen-Hua Yu

发明人： Tsu Shih ,  Jui-Yu Chang ,  Syun-Ming Jang ,  Chen-Hua Yu

IPC分类号： G03F9/00 ,  H01L23/544 ,  H01L23/48

CPC分类号： G03F9/708 ,  G03F9/7084 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2223/54493 ,  H01L2924/0002

摘要： A method for forming alignment marks are disclosed for performing photoalignment after chemical-mechanical polishing (CMP). A trench is first formed in a silicon substrate and then alignment marks are formed at the bottom of the trench. The aspect ratio of the trench is selected to be so low that the dishing of the CMP pad can be prevented from reaching into the trench to damage the alignment marks therein. A trench structure is also provided whereby the alignment marks can be protected from the abrasive action of the CMP. Steps subsequent to the CMP can therefore proceed unimpeded with the presence of undamaged alignment marks.

公开(公告)号：US5933744A

公开(公告)日：1999-08-03

申请号：US54302

申请日：1998-04-02

申请人： Jeng-Horng Chen ,  Tsu Shih ,  Jui-Yu Chang ,  Chung-Long Chang

发明人： Jeng-Horng Chen ,  Tsu Shih ,  Jui-Yu Chang ,  Chung-Long Chang

IPC分类号： H01L21/3105 ,  H01L23/544 ,  H01L21/465 ,  H01L21/76

CPC分类号： H01L23/544 ,  H01L21/31053 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975

摘要： A method of alignment for a chemical mechanical polishing includes previously patterning a primary zero alignment mark on a surface of a wafer. A first dielectric layer is deposited on the wafer for isolation. Then, an etching is used to etch the first dielectric layer using a photoresist as a mask. First conductive plugs are formed in the first dielectric layer. Next, a first conductive layer is formed on the surface of the first dielectric layer and on the tungsten plugs. Thus, the first non-zero alignment mark pattern is formed on the surface of the first conductive layer and aligned to the first conductive plugs. Next, a second non-zero alignment mark pattern is thus formed on the surface of a second conductive layer and aligned to the a second conductive plugs. By repeating the aforementioned method, odd non-zero alignment mark patterns will be formed over the first non-zero alignment mark pattern, and even non-zero alignment mark patterns will be formed over the second non-zero alignment mark pattern. Therefore, the present invention save space to put non-zero alignment marks in multilevel interconnection and planarization processes.

摘要翻译： 用于化学机械抛光的对准方法包括预先对晶片表面上的初级零对准标记进行图案化。 第一介电层沉积在晶片上用于隔离。 然后，使用蚀刻来使用光致抗蚀剂作为掩模蚀刻第一介电层。 在第一电介质层中形成第一导电插塞。 接下来，在第一电介质层的表面和钨插塞上形成第一导电层。 因此，第一非零对准标记图案形成在第一导电层的表面上并与第一导电插塞对准。 接下来，在第二导电层的表面上形成第二非零对准标记图案，并与第二导电插塞对准。 通过重复上述方法，将在第一非零对准标记图案上形成奇数非零对准标记图案，并且甚至在第二非零对准标记图案上形成非零对准标记图案。 因此，本发明节省空间，将非零对准标记放置在多层互连和平面化处理中。

公开(公告)号：US5923996A

公开(公告)日：1999-07-13

申请号：US867312

申请日：1997-06-02

申请人： Tsu Shih ,  Jui-Yu Chang ,  Syun-Ming Jang ,  Chen-Hua Yu

发明人： Tsu Shih ,  Jui-Yu Chang ,  Syun-Ming Jang ,  Chen-Hua Yu

IPC分类号： H01L23/544 ,  H01L21/46 ,  H01L21/301 ,  H01L21/78

CPC分类号： H01L23/544 ,  H01L2223/5442 ,  H01L2223/54493 ,  H01L2924/0002

摘要： A method is disclosed for forming alignment marks at the outer perimeter of wafers where they are not susceptible to much damage during chemical-mechanical polishing (CMP) process. Complete protection is provided by recessing the alignment mark into the substrate by etching. Recess etching is accomplished at the same time the isolation trenches are followed to delineate device areas. Thus, alignment marks are provided with a protective recess without extra steps. Furthermore, by forming alignment marks at the outer perimeter of the wafer, productivity is improved by providing maximum usage of wafer area for integrated circuits.

摘要翻译： 公开了一种用于在晶片的外周边形成对准标记的方法，其中它们在化学机械抛光（CMP）工艺期间不会受到很大的损害。 通过蚀刻将对准标记凹入衬底来提供完整的保护。 在同时完成凹槽蚀刻，同时遵循隔离沟以描绘器件区域。 因此，对准标记设置有保护凹槽而没有额外的步骤。 此外，通过在晶片的外周形成对准标记，通过提供用于集成电路的晶片面积的最大使用来提高生产率。

公开(公告)号：US06686284B2

公开(公告)日：2004-02-03

申请号：US10072244

申请日：2002-02-06

申请人： Chi-Wei Chung ,  Tung-Ching Tseng ,  Tsu Shih ,  Syun-Ming Jang

发明人： Chi-Wei Chung ,  Tung-Ching Tseng ,  Tsu Shih ,  Syun-Ming Jang

IPC分类号： H01L2100

CPC分类号： H01L21/3212 ,  B24B37/32 ,  B24B55/02 ,  H01L21/31053

摘要： A chemical mechanical polishing apparatus that is equipped with a chilled retaining ring and a method for using the apparatus are described. The retaining ring is mounted therein a heat transfer means such as a metal tube and flowing therethrough a heat exchanging fluid for carrying away heat from the wafer mounted in the retaining ring, resulting in a temperature reduction in the slurry solution that contacts the wafer. The present invention apparatus and method therefore reduces the delamination problem for low k dielectric materials during polishing and the wafer scratching problem.

摘要翻译： 描述了配备有冷冻保持环的化学机械抛光装置和使用该装置的方法。 保持环安装有诸如金属管的传热装置，并在其中流过用​​于从安装在保持环中的晶片携带热量的热交换流体，导致与晶片接触的浆液中的温度降低。 因此，本发明的装置和方法减少了抛光期间低k电介质材料和晶片划伤问题的分层问题。

公开(公告)号：US06638868B1

公开(公告)日：2003-10-28

申请号：US10141221

申请日：2002-05-07

申请人： Tsu Shih ,  Kun Ku Hung ,  Wen-Hun Tung ,  Wen-Chin Chiou

发明人： Tsu Shih ,  Kun Ku Hung ,  Wen-Hun Tung ,  Wen-Chin Chiou

IPC分类号： H01L21302

CPC分类号： B24B37/046 ,  B24B37/042 ,  H01L21/02071 ,  H01L21/3212 ,  H01L21/7684

摘要： A method and apparatus for implementing the method for preventing or reducing corrosion of copper containing features included in a semiconductor wafer in a chemical mechanical polishing (CMP) process the method providing at least one semiconductor wafer polishing surface including copper filled anisotropically etched features; polishing the at least one semiconductor wafer polishing surface according to a CMP process having a polishing pad surface contacting the at least one it semiconductor wafer polishing surface at least a portion of the polishing pad in electrically conductive communication with a conductive polishing platen; and, providing at least one electrically conductive pathway from the conductive polishing platen.

摘要翻译： 一种用于在化学机械抛光（CMP）工艺中实现用于防止或减少包含在半导体晶片中的含铜特征的腐蚀的方法和装置，该方法提供至少一个包括铜填充的各向异性蚀刻特征的半导体晶片抛光表面的方法; 根据CMP工艺抛光所述至少一个半导体晶片抛光表面，所述CMP工艺具有抛光垫表面，所述抛光垫表面与所述至少一个半导体晶片抛光表面接触，所述至少一部分所述抛光垫与导电抛光平台导电连通; 以及从所述导电抛光平台提供至少一个导电通路。

公开(公告)号：US06620034B2

公开(公告)日：2003-09-16

申请号：US10043780

申请日：2002-01-14

申请人： Tsu Shih ,  Jih-Churng Jwu ,  Ying-Ho Chen ,  Syun-Ming Jang

发明人： Tsu Shih ,  Jih-Churng Jwu ,  Ying-Ho Chen ,  Syun-Ming Jang

IPC分类号： B24B100

CPC分类号： B24B37/12 ,  B24B37/015 ,  B24B55/02

摘要： The invention provides a method and an apparatus that prevent the accumulation of copper ions during CMP of copper lines by performing the CMP process at low temperatures and by maintaining this low temperature during the CMP process by adding a slurry that functions as a corrosion inhibitor.

摘要翻译： 本发明提供了一种方法和装置，其通过在低温下进行CMP工艺，并且通过添加用作腐蚀抑制剂的浆料在CMP工艺期间保持该低温来防止铜线的CMP中的铜离子的累积。

公开(公告)号：US06602780B2

公开(公告)日：2003-08-05

申请号：US09947788

申请日：2001-09-06

申请人： Tsu Shih ,  Yung-Cheng Lu ,  Lih Ping Li ,  Tien-I Bao ,  Chung Chi Ko

发明人： Tsu Shih ,  Yung-Cheng Lu ,  Lih Ping Li ,  Tien-I Bao ,  Chung Chi Ko

IPC分类号： H01L214763

CPC分类号： H01L21/76807 ,  H01L21/76831 ,  H01L2221/1057

摘要： A method for forming a protective oxide liner to reduce a surface reflectance including providing a hydrophilic insulating layer over a conductive layer; providing an anti-reflectance coating (ARC) layer over the hydrophilic insulating layer; providing an etching stop layer over the anti-reflectance coating (ARC) layer; photolithographically defining a pattern on a surface of the etching stop layer for etching; anisotropically etching at least one etch opening extending at least partially through a thickness of the hydrophilic insulating layer; depositing an oxide liner such that the sidewalls and bottom portion of the at least one etch opening and said surface are covered by the oxide liner; and, removing the oxide liner from aid surface according to a chemical mechanical (CMP) process to a surface reflectance.

摘要翻译： 一种用于形成保护性氧化物衬垫以减少表面反射率的方法，包括在导电层上提供亲水性绝缘层; 在所述亲水绝缘层上提供抗反射涂层（ARC）层; 在抗反射涂层（ARC）层上提供蚀刻停止层; 在蚀刻停止层的表面上光刻地限定图案用于蚀刻; 各向异性蚀刻至少一个至少部分延伸穿过亲水性绝缘层的厚度的蚀刻开口; 沉积氧化物衬里，使得所述至少一个蚀刻开口和所述表面的侧壁和底部被所述氧化物衬垫覆盖; 并且根据化学机械（CMP）工艺将氧化物衬垫从辅助表面去除到表面反射率。