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    Scribe-line structures and methods of forming the same
    2.
    发明申请
    Scribe-line structures and methods of forming the same 有权
    划线结构及其形成方法

    公开(公告)号：US20060163701A1

    公开(公告)日：2006-07-27

    申请号：US11335359

    申请日：2006-01-19

    申请人： Jeong-Hoon Ahn ,  Heon-Jong Shin

    发明人： Jeong-Hoon Ahn ,  Heon-Jong Shin

    IPC分类号： H01L23/544

    CPC分类号： H01L23/3192 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/3025 ,  H01L2924/00

    摘要： Scribe-line structures and methods of forming such scribe-line structures on a face of a semiconductor substrate are provided. By means of the scribe-line structures and the methods of this invention, physical shock and cracking tendencies along a semiconductor substrate can be minimized during performance of a cutting process on the semiconductor substrate as part of post-fabrication processing. A representative method according to this invention comprises the sequential steps of: forming a lower layer on a semiconductor substrate; forming a molding layer on the lower layer such that the molding layer includes at least one protective contact hole; subsequently forming a dielectric layer and an upper layer on the molding layer so as to fill the protective contact hole, such dielectric layer being formed of a material having a greater mechanical intensity than that of the molding layer; and then forming protective layer patterns on the upper layer.

    摘要翻译： 提供了在半导体衬底的表面上形成这种划线结构的划线结构和方法。 通过本发明的划线结构和方法，作为后制造处理的一部分，在半导体衬底上的切割过程中执行切割过程期间，半导体衬底的物理冲击和开裂倾向可以最小化。 根据本发明的代表性方法包括以下顺序步骤：在半导体衬底上形成下层; 在所述下层上形成模塑层，使得所述模制层包括至少一个保护性接触孔; 随后在成型层上形成电介质层和上层以便填充保护接触孔，这种电介质层由具有比模塑层的机械强度更大的机械强度的材料形成; 然后在上层形成保护层图案。

    Scribe-line structures and methods of forming the same
    3.
    发明授权
    Scribe-line structures and methods of forming the same 有权
    划线结构及其形成方法

    公开(公告)号：US07358155B2

    公开(公告)日：2008-04-15

    申请号：US11335359

    申请日：2006-01-19

    申请人： Jeong-Hoon Ahn ,  Heon-Jong Shin

    发明人： Jeong-Hoon Ahn ,  Heon-Jong Shin

    IPC分类号： H01L21/00

    CPC分类号： H01L23/3192 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/3025 ,  H01L2924/00

    摘要： Scribe-line structures and methods of forming such scribe-line structures on a face of a semiconductor substrate are provided. By means of the scribe-line structures and the methods of this invention, physical shock and cracking tendencies along a semiconductor substrate can be minimized during performance of a cutting process on the semiconductor substrate as part of post-fabrication processing. A representative method according to this invention comprises the sequential steps of: forming a lower layer on a semiconductor substrate; forming a molding layer on the lower layer such that the molding layer includes at least one protective contact hole; subsequently forming a dielectric layer and an upper layer on the molding layer so as to fill the protective contact hole, such dielectric layer being formed of a material having a greater mechanical intensity than that of the molding layer; and then forming protective layer patterns on the upper layer.

    摘要翻译： 提供了在半导体衬底的表面上形成这种划线结构的划线结构和方法。 通过本发明的划线结构和方法，作为后制造处理的一部分，在半导体衬底上的切割过程的执行过程中，半导体衬底的物理冲击和开裂倾向可以最小化。 根据本发明的代表性方法包括以下顺序步骤：在半导体衬底上形成下层; 在所述下层上形成模塑层，使得所述模制层包括至少一个保护性接触孔; 随后在成型层上形成电介质层和上层以便填充保护接触孔，这种电介质层由具有比模塑层的机械强度更大的机械强度的材料形成; 然后在上层形成保护层图案。

    SCRIBE-LINE STRUCTURES AND METHODS OF FORMING THE SAME
    4.
    发明申请
    SCRIBE-LINE STRUCTURES AND METHODS OF FORMING THE SAME 审中-公开
    SCRIBE-LINE结构及其形成方法

    公开(公告)号：US20080142927A1

    公开(公告)日：2008-06-19

    申请号：US12034919

    申请日：2008-02-21

    申请人： Jeong-Hoon Ahn ,  Heon-Jong Shin

    发明人： Jeong-Hoon Ahn ,  Heon-Jong Shin

    IPC分类号： H01L23/544

    CPC分类号： H01L23/3192 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/3025 ,  H01L2924/00

    摘要： Scribe-line structures and methods of forming such scribe-line structures on a face of a semiconductor substrate are provided. By means of the scribe-line structures and the methods of this invention, physical shock and cracking tendencies along a semiconductor substrate can be minimized during performance of a cutting process on the semiconductor substrate as part of post-fabrication processing. A representative method according to this invention comprises the sequential steps of: forming a lower layer on a semiconductor substrate; forming a molding layer on the lower layer such that the molding layer includes at least one protective contact hole; subsequently forming a dielectric layer and an upper layer on the molding layer so as to fill the protective contact hole, such dielectric layer being formed of a material having a greater mechanical intensity than that of the molding layer; and then forming protective layer patterns on the upper layer.

    摘要翻译： 提供了在半导体衬底的表面上形成这种划线结构的划线结构和方法。 通过本发明的划线结构和方法，作为后制造处理的一部分，在半导体衬底上的切割过程的执行过程中，半导体衬底的物理冲击和开裂倾向可以最小化。 根据本发明的代表性方法包括以下顺序步骤：在半导体衬底上形成下层; 在所述下层上形成模塑层，使得所述模制层包括至少一个保护性接触孔; 随后在成型层上形成电介质层和上层以便填充保护接触孔，这种电介质层由具有比模塑层的机械强度更大的机械强度的材料形成; 然后在上层形成保护层图案。

    Metal line structures and methods of forming the same
    5.
    发明申请
    Metal line structures and methods of forming the same 审中-公开
    金属线结构及其形成方法

    公开(公告)号：US20080048339A1

    公开(公告)日：2008-02-28

    申请号：US11892226

    申请日：2007-08-21

    申请人： Jeong-Hoon Ahn ,  Heon-Jong Shin

    发明人： Jeong-Hoon Ahn ,  Heon-Jong Shin

    IPC分类号： H01L23/528 ,  H01L21/4763

    CPC分类号： H01L23/53223 ,  H01L21/76807 ,  H01L21/76843 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Example embodiments may provide metal line structures, and example methods may include forming the same. Example embodiment metal line structures may include a first metal line on a substrate, a first barrier metal layer on sidewalls and a lower surface of the first metal line, a first insulating layer covering the first metal line, a second metal line on the first insulating layer, a contact plug passing through the first insulating layer to electrically connect the first metal line and the second metal line, and a second barrier metal layer on sidewalls and a lower surface of the contact plug and the second metal line. The first barrier metal layer and the second barrier metal layer may contact each other.

    摘要翻译： 示例性实施例可以提供金属线结构，并且示例性方法可以包括形成它们。 示例性实施例金属线结构可以包括衬底上的第一金属线，侧壁上的第一阻挡金属层和第一金属线的下表面，覆盖第一金属线的第一绝缘层，第一绝缘层上的第二金属线 层，通过第一绝缘层的接触插塞以电连接第一金属线和第二金属线，以及在接触插塞和第二金属线的侧壁和下表面上的第二阻挡金属层。 第一阻挡金属层和第二阻挡金属层可以彼此接触。

    Shared contact structure, semiconductor device and method of fabricating the semiconductor device
    8.
    发明授权
    Shared contact structure, semiconductor device and method of fabricating the semiconductor device 有权
    共享接触结构，半导体器件和制造半导体器件的方法

    公开(公告)号：US07781282B2

    公开(公告)日：2010-08-24

    申请号：US11377455

    申请日：2006-03-17

    申请人： Abraham Yoo ,  Hee-Sung Kang ,  Heon-Jong Shin

    发明人： Abraham Yoo ,  Hee-Sung Kang ,  Heon-Jong Shin

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/6656 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/51 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659

    摘要： A shared contact structure, semiconductor device and method of fabricating the semiconductor device, in which the shared contact structure may include a gate electrode disposed on an active region of a substrate and including facing first and second sidewalls. The first sidewall may be covered with an insulating spacer. The source/drain regions may be formed within the active region adjacent the first sidewall, and provided on the opposite side of the second sidewall. A corner protection pattern may be formed adjacent the source/drain regions and the insulating spacer, and covered by an inter-layer dielectric. A shared contact plug may be formed through the inter-layer dielectric, to be in contact with the gate electrode, corner protection pattern and source/drain regions.

    摘要翻译： 共享接触结构，半导体器件和制造半导体器件的方法，其中共享接触结构可以包括设置在衬底的有源区上并包括相对的第一和第二侧壁的栅电极。 第一侧壁可以被绝缘间隔物覆盖。 源极/漏极区域可以形成在与第一侧壁相邻的有源区域内，并且设置在第二侧壁的相对侧上。 可以在源极/漏极区域和绝缘间隔物附近形成角保护图案，并且被层间电介质覆盖。 可以通过层间电介质形成共同的接触插塞，以与栅电极，角保护图案和源极/漏极区域接触。

    MOS transistor for high-speed and high-performance operation and manufacturing method thereof
    9.
    发明授权
    MOS transistor for high-speed and high-performance operation and manufacturing method thereof 有权
    MOS晶体管用于高速和高性能的操作及制造方法

    公开(公告)号：US06274906B1

    公开(公告)日：2001-08-14

    申请号：US09198230

    申请日：1998-11-23

    申请人： Hyun-Sik Kim ,  Heon-Jong Shin ,  Soo-Cheol Lee

    发明人： Hyun-Sik Kim ,  Heon-Jong Shin ,  Soo-Cheol Lee

    IPC分类号： H01L2976

    CPC分类号： H01L29/6659 ,  H01L29/1083 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7836 ,  Y10S257/90

    摘要： A MOS transistor of the present invention includes a semiconductor substrate of a first conductivity type impurity, a gate insulating layer formed on the semiconductor substrate, gate electrodes formed on the gate insulating layer, and an oxide layer formed by surface oxidation of the gate electrodes. A first spacer is formed on the side wall of the gate electrodes, and a second spacer is formed on the inclined side wall. A first impurity layer of low concentration is formed at a first depth by a second conductivity type impurity implanted in the vicinity of surface of the semiconductor substrate to be self-aligned at the edge of the gate electrode. A second impurity layer of middle concentration is formed at a deeper second depth than the first depth by the second conductivity type impurity implanted in the vicinity of surface of the semiconductor substrate. A third impurity layer having higher impurity concentration than that of the semiconductor, is formed at a third depth for surrounding the second impurity layer of middle concentration by a first conductivity type impurity implanted in the vicinity of surface of the semiconductor substrate to be self-aligned at the edge of the first spacer. A fourth impurity layer of high concentration formed at a fourth depth deeper than the third depth by the second conductivity type impurity implanted in the vicinity of the surface of the semiconductor substrate to be aligned at the edge of the second spacer.

    摘要翻译： 本发明的MOS晶体管包括第一导电型杂质的半导体衬底，形成在半导体衬底上的栅极绝缘层，形成在栅极绝缘层上的栅电极和通过栅电极的表面氧化形成的氧化物层。 第一间隔件形成在栅电极的侧壁上，第二间隔件形成在倾斜侧壁上。 通过注入在半导体衬底的表面附近的第二导电类型的杂质在第一深度处形成低浓度的第一杂质层，以在栅电极的边缘处自对准。 通过注入在半导体衬底的表面附近的第二导电类型杂质，在比第一深度更深的第二深度处形成中等浓度的第二杂质层。 在第三深度形成第三杂质层，该第三杂质层通过注入在半导体衬底的表面附近的第一导电型杂质包围中间浓度的第二杂质层以进行自对准 在第一间隔物的边缘。 通过注入在半导体衬底的表面附近的第二导电类型杂质在第二深度上比第三深度更深的第四深度形成第四杂质层，以在第二间隔物的边缘对齐。

    Semiconductor device having spacer and method of making same
    10.
    发明授权
    Semiconductor device having spacer and method of making same 失效
    具有双重间隔物的半导体器件及其制造方法

    公开(公告)号：US5929483A

    公开(公告)日：1999-07-27

    申请号：US113624

    申请日：1998-07-10

    申请人： Hyun-Sik Kim ,  Heon-Jong Shin

    发明人： Hyun-Sik Kim ,  Heon-Jong Shin

    IPC分类号： H01L29/78 ,  H01L21/22 ,  H01L21/336 ,  H01L27/088 ,  H01L29/10

    CPC分类号： H01L29/6659 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/6656 ,  H01L29/665 ,  H01L29/7833 ,  Y10S257/90

    摘要： A semiconductor device having a double spacer and a method of manufacturing the device are provided. The semiconductor device includes a first spacer formed on the sidewall of a gate electrode and a second spacer formed on the slanted sidewall of the first spacer. A first impurity region is formed doped with a first conductivity type impurity at a first concentration and formed at a small junction depth in the substrate to self-align at the edge of the gate electrode. A second impurity region doped with a second conductivity type impurity at a second concentration is formed at a large junction depth in the substrate to self-align at the edge of the first spacer. A third impurity region doped with the first conductivity type impurity at a third concentration is formed at a medium junction depth in the second impurity region to self-align at the edge of the second spacer.

    摘要翻译： 提供了具有双间隔物的半导体器件及其制造方法。 半导体器件包括形成在栅电极的侧壁上的第一间隔物和形成在第一间隔物的倾斜侧壁上的第二间隔物。 第一杂质区被形成为掺杂有第一浓度的第一导电型杂质并且形成在衬底中的小结深处以在栅电极的边缘处自对准。 在第二浓度下掺杂有第二导电类型杂质的第二杂质区域形成在衬底中的大的结深处，以在第一间隔物的边缘处自对准。 在第二杂质区域的中间结深处形成掺杂有第三浓度的第一导电型杂质的第三杂质区域，以在第二间隔物的边缘处自对准。