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1.发明授权Method for efficiently executing video encoding operations on stream processor architectures 有权用于在流处理器架构上有效执行视频编码操作的方法公开(公告)号：US08437407B2
公开(公告)日：2013-05-07
申请号：US13463526
申请日：2012-05-03
IPC分类号： H04N7/12
CPC分类号： H04N19/436
摘要： Techniques are disclosed for employing a set of stream processors to greatly accelerate common video encoding and transcoding tasks, with the goal of making these tasks run at a reasonable rate on off-the-shelf hardware. Stream processors are most commonly found in the graphics processing unit (GPU), a commodity piece of computer hardware used to generate images for display. Embodiments of the invention are particularly advantageous to accelerate video encoding and transcoding tasks in which the blocks being processed have dependencies on their neighboring blocks.
摘要翻译： 公开了采用一组流处理器来大大加速公共视频编码和代码转换任务的技术，目的是使这些任务在现成的硬件上以合理的速率运行。 流处理器最常见于图形处理单元（GPU）中，该处理单元是用于生成用于显示的图像的计算机硬件的商品。 本发明的实施例特别有利于加速视频编码和代码转换任务，其中被处理的块依赖于它们的相邻块。
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公开(公告)号：US20090125538A1
公开(公告)日：2009-05-14
申请号：US12058636
申请日：2008-03-28
CPC分类号： G06F15/8007 , H04N19/174 , H04N19/176 , H04N19/436 , H04N19/44 , H04N19/91
摘要： A method is disclosed for the decoding and encoding of a block-based video bit-stream such as MPEG2, H.264-AVC, VC1, or VP6 using a system containing one or more high speed sequential processors, a homogenous array of software configurable general purpose parallel processors, and a high speed memory system to transfer data between processors or processor sets. This disclosure includes a method for load balancing between the two sets of processors.
摘要翻译： 公开了一种用于使用包含一个或多个高速顺序处理器的系统对诸如MPEG2，H.264-AVC，VC1或VP6的基于块的视频比特流进行解码和编码的方法，软件可组态的均匀阵列 通用并行处理器和用于在处理器或处理器组之间传输数据的高速存储器系统。 本公开包括用于两组处理器之间的负载平衡的方法。
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3.发明申请METHOD FOR EFFICIENTLY EXECUTING VIDEO ENCODING OPERATIONS ON STREAM PROCESSOR ARCHITECTURES 有权有效执行流水线处理器架构视频编码操作的方法公开(公告)号：US20120219068A1
公开(公告)日：2012-08-30
申请号：US13463526
申请日：2012-05-03
IPC分类号： H04N7/24
CPC分类号： H04N19/436
摘要： Techniques are disclosed for employing a set of stream processors to greatly accelerate common video encoding and transcoding tasks, with the goal of making these tasks run at a reasonable rate on off-the-shelf hardware. Stream processors are most commonly found in the graphics processing unit (GPU), a commodity piece of computer hardware used to generate images for display. Embodiments of the invention are particularly advantageous to accelerate video encoding and transcoding tasks in which the blocks being processed have dependencies on their neighboring blocks.
摘要翻译： 公开了采用一组流处理器来大大加速公共视频编码和代码转换任务的技术，目的是使这些任务在现成的硬件上以合理的速率运行。 流处理器最常见于图形处理单元（GPU）中，该处理单元是用于生成用于显示的图像的计算机硬件的商品。 本发明的实施例特别有利于加速视频编码和代码转换任务，其中被处理的块依赖于它们的相邻块。
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4.发明授权Method for efficiently executing video encoding operations on stream processor architectures 有权用于在流处理器架构上有效执行视频编码操作的方法公开(公告)号：US08184715B1
公开(公告)日：2012-05-22
申请号：US12189735
申请日：2008-08-11
IPC分类号： H04N11/02
CPC分类号： H04N19/436
摘要： Techniques are disclosed for employing a set of stream processors to greatly accelerate common video encoding and transcoding tasks, with the goal of making these tasks run at a reasonable rate on off-the-shelf hardware. Stream processors are most commonly found in the graphics processing unit (GPU), a commodity piece of computer hardware used to generate images for display. Embodiments of the invention are particularly advantageous to accelerate video encoding and transcoding tasks in which the blocks being processed have dependencies on their neighboring blocks.
摘要翻译： 公开了采用一组流处理器来大大加速公共视频编码和代码转换任务的技术，目的是使这些任务在现成的硬件上以合理的速率运行。 流处理器最常见于图形处理单元（GPU）中，该处理单元是用于生成用于显示的图像的计算机硬件的商品。 本发明的实施例特别有利于加速视频编码和代码转换任务，其中被处理的块依赖于它们的相邻块。
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公开(公告)号：US20120093234A1
公开(公告)日：2012-04-19
申请号：US13314013
申请日：2011-12-07
IPC分类号： H04N7/32
CPC分类号： G06F15/8007 , H04N19/174 , H04N19/176 , H04N19/436 , H04N19/44 , H04N19/91
摘要： A method is disclosed for the decoding and encoding of a block-based video bit-stream such as MPEG2, H.264-AVC, VC1, or VP6 using a system containing one or more high speed sequential processors, a homogenous array of software configurable general purpose parallel processors, and a high speed memory system to transfer data between processors or processor sets. This disclosure includes a method for load balancing between the two sets of processors.
摘要翻译： 公开了一种用于使用包含一个或多个高速顺序处理器的系统对诸如MPEG2，H.264-AVC，VC1或VP6的基于块的视频比特流进行解码和编码的方法，软件可组态的均匀阵列 通用并行处理器和用于在处理器或处理器组之间传输数据的高速存储器系统。 本公开包括用于两组处理器之间的负载平衡的方法。
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公开(公告)号：US09747251B2
公开(公告)日：2017-08-29
申请号：US13314013
申请日：2011-12-07
IPC分类号： H04N19/44 , G06F15/80 , H04N19/176 , H04N19/91 , H04N19/174 , H04N19/436
CPC分类号： G06F15/8007 , H04N19/174 , H04N19/176 , H04N19/436 , H04N19/44 , H04N19/91
摘要： A method is disclosed for the decoding and encoding of a block-based video bit-stream such as MPEG2, H.264-AVC, VC1, or VP6 using a system containing one or more high speed sequential processors, a homogenous array of software configurable general purpose parallel processors, and a high speed memory system to transfer data between processors or processor sets. This disclosure includes a method for load balancing between the two sets of processors.
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公开(公告)号：US08121197B2
公开(公告)日：2012-02-21
申请号：US12058636
申请日：2008-03-28
IPC分类号： H04N7/12
CPC分类号： G06F15/8007 , H04N19/174 , H04N19/176 , H04N19/436 , H04N19/44 , H04N19/91
摘要： A method is disclosed for the decoding and encoding of a block-based video bit-stream such as MPEG2, H.264-AVC, VC1, or VP6 using a system containing one or more high speed sequential processors, a homogenous array of software configurable general purpose parallel processors, and a high speed memory system to transfer data between processors or processor sets. This disclosure includes a method for load balancing between the two sets of processors.
摘要翻译： 公开了一种用于使用包含一个或多个高速顺序处理器的系统对诸如MPEG2，H.264-AVC，VC1或VP6的基于块的视频比特流进行解码和编码的方法，软件可组态的均匀阵列 通用并行处理器和用于在处理器或处理器组之间传输数据的高速存储器系统。 本公开包括用于两组处理器之间的负载平衡的方法。
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公开(公告)号：US08542732B1
公开(公告)日：2013-09-24
申请号：US12342145
申请日：2008-12-23
CPC分类号： G06T1/60 , G06T1/20 , G09G2360/125 , H04N19/423 , H04N19/433 , H04N19/436 , H04N19/513
摘要： An apparatus comprising a graphics processing unit, a processor and a memory. The memory stores computer executable instructions. The computer executable instructions use (i) the graphics processing unit to perform prediction, decimation, transformation and quantization, and inverse-quantization and inverse-transformation and (ii) the processor to perform entropy encoding and rate control.
摘要翻译： 一种包括图形处理单元，处理器和存储器的装置。 存储器存储计算机可执行指令。 计算机可执行指令使用（i）图形处理单元执行预测，抽取，变换和量化，逆量化和逆变换，以及（ii）处理器执行熵编码和速率控制。
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公开(公告)号：US09462019B1
公开(公告)日：2016-10-04
申请号：US13467397
申请日：2012-05-09
申请人： Jesse J. Rosenzweig
发明人： Jesse J. Rosenzweig
IPC分类号： H04L29/06 , H04L12/853
CPC分类号： H04L65/4092 , H04L41/5032 , H04L41/5038 , H04L41/5067 , H04L43/50 , H04L47/2416 , H04L65/4076 , H04L65/80 , H04L67/02 , H04L67/22
摘要： A system comprising a broadcast facility, one or more players, and an analytic service center. The broadcast facility may be configured to provide a plurality of streams. The one or more players may be configured to receive at least one of the plurality of streams and provide feedback on a user experience. The analytic service center may be configured to receive the feedback from the one or more players.
摘要翻译： 一种包括广播设施，一个或多个播放器和分析服务中心的系统。 广播设施可以被配置为提供多个流。 一个或多个玩家可以被配置为接收多个流中的至少一个并且提供关于用户体验的反馈。 分析服务中心可以被配置为从一个或多个玩家接收反馈。
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公开(公告)号：US08374242B1
公开(公告)日：2013-02-12
申请号：US13104225
申请日：2011-05-10
CPC分类号： G06T1/60 , G06T1/20 , G09G2360/125 , H04N19/423 , H04N19/433 , H04N19/436 , H04N19/513
摘要： An apparatus includes a processor, a graphics processing unit and a memory. The memory stores computer executable instructions. The computer executable instructions include a motion estimation kernel which when executed by the graphics processing unit performs motion estimation on a current frame using a reference frame. The current frame and the reference frame are stored in a globally shared memory of the graphics processing unit.
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