公开(公告)号：US20060055043A1

公开(公告)日：2006-03-16

申请号：US10939931

申请日：2004-09-13

申请人： Jhon Liaw ,  Sung-Chun Hsieh ,  Wesley Lin ,  Chii-Ming Wu ,  Ren-Fen Tsui

发明人： Jhon Liaw ,  Sung-Chun Hsieh ,  Wesley Lin ,  Chii-Ming Wu ,  Ren-Fen Tsui

IPC分类号： H01L29/40

CPC分类号： H01L21/76843 ,  H01L21/76816 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure relates generally to the manufacturing of semiconductor devices, and more particularly to an improved connection structure for semiconductor devices. A connection structure for a semiconductor device includes: a peanut-shaped opening comprising a narrow area and one or more wide areas, wherein the narrow area is between two of the one or more wide areas; and a conductive plug for filling at least partially the peanut-shaped opening.

摘要翻译： 本公开一般涉及半导体器件的制造，更具体地，涉及用于半导体器件的改进的连接结构。 半导体器件的连接结构包括：花生形开口，其包括狭窄区域和一个或多个宽阔区域，其中所述狭窄区域在所述一个或多个宽区域中的两个之间; 以及用于至少部分地填充花生形开口的导电插塞。

公开(公告)号：US20050085081A1

公开(公告)日：2005-04-21

申请号：US10687424

申请日：2003-10-16

申请人： Jhon Liaw

发明人： Jhon Liaw

IPC分类号： H01L21/302 ,  H01L21/306 ,  H01L21/336 ,  H01L21/461 ,  H01L21/84 ,  H01L27/12 ,  H01L29/45 ,  H01L29/786

CPC分类号： H01L29/66772 ,  H01L21/02046 ,  H01L21/02052 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/458 ,  H01L29/7842 ,  H01L29/78687

摘要： A method of manufacturing a microelectronics device including providing a substrate having an active layer, a dielectric layer and a structural layer, wherein the active layer is formed over the dielectric layer and the dielectric layer is formed over the structural layer. The method further includes forming an opening through the active layer thereby exposing a surface of the dielectric layer and defining active layer sidewalls. A spacer is formed covering a first portion of the exposed dielectric layer surface and substantially spanning one of the active layer sidewalls. At least a second portion of the exposed dielectric layer surface is then cleaned.

摘要翻译： 一种制造微电子器件的方法，包括提供具有有源层，电介质层和结构层的衬底，其中所述有源层形成在所述电介质层上，并且所述电介质层形成在所述结构层上。 该方法还包括通过有源层形成开口，从而暴露电介质层的表面并限定活性层侧壁。 形成覆盖暴露的电介质层表面的第一部分并且基本跨越有源层侧壁之一的间隔物。 然后清洁暴露的电介质层表面的至少第二部分。

公开(公告)号：US20060239066A1

公开(公告)日：2006-10-26

申请号：US10907978

申请日：2005-04-22

申请人： Jhon Liaw

发明人： Jhon Liaw

IPC分类号： G11C11/14

CPC分类号： G11C11/15

摘要： A memory device includes a memory cell, a reference structure, and a sensing device. The memory cell includes an MR element and a pass transistor. The pass transistor, reference structure, and sensing device are connected to an input node. The logic state of the memory cell can be detected by a read operation that includes the sensing device sensing the voltage at the input node. The voltage at the input node will vary depending on the state of the MR element. The reference structure provides a voltage drop allowing for an increased read voltage to the memory cell. This in turn can provide for decreased read times. In some embodiments, the MR element can include a magnetic tunneling junction sandwiched between electrode layers. One of the electrode layers can be connected to a bit line, the other can be connected to the pass transistor.

摘要翻译： 存储器件包括存储器单元，参考结构和感测装置。 存储单元包括MR元件和通过晶体管。 传输晶体管，参考结构和感测设备连接到输入节点。 存储器单元的逻辑状态可以通过读取操作来检测，该读取操作包括检测输入节点处的电压的感测装置。 输入节点处的电压将根据MR元件的状态而变化。 参考结构提供了允许增加对存储器单元的读取电压的电压降。 这又可以减少读取时间。 在一些实施例中，MR元件可以包括夹在电极层之间的磁性隧道结。 一个电极层可以连接到位线，另一个可以连接到传输晶体管。

公开(公告)号：US20060091468A1

公开(公告)日：2006-05-04

申请号：US10982455

申请日：2004-11-04

申请人： Jhon Liaw

发明人： Jhon Liaw

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76895 ,  H01L27/0207 ,  H01L27/1104

摘要： An interconnect structure and its method for fabrication each employ an interconnect formed over and adjacent an active region of a semiconductor substrate. A gate electrode is also formed over the active region. Spacer layers are formed adjoining the interconnect and the gate electrode. A spacer layer adjoining the interconnect is removed and a bridging silicide conductor layer is formed bridging a top surface and a sidewall surface of the interconnect with a surface of the active region.

摘要翻译： 互连结构及其制造方法各自采用在半导体衬底的有源区上方形成的相互连接。 栅电极也形成在有源区上。 形成邻接互连和栅电极的间隔层。 去除与互连件邻接的间隔层，并且形成桥接硅化物导体层，桥接互连的顶表面和侧壁表面与有源区的表面。

公开(公告)号：US20070127287A1

公开(公告)日：2007-06-07

申请号：US11699189

申请日：2007-01-29

申请人： Jhon Liaw

发明人： Jhon Liaw

IPC分类号： G11C11/00

CPC分类号： G11C11/4125

摘要： A memory cell for reducing soft error rate and the method for forming same are disclosed. The memory cell comprises a first bit line signal (BL), a second bit line signal complementary to the first bit line signal (BLB), a first pass gate coupled to the BL, a second pass gate coupled to the BLB, a first inverter whose output node receives the BL through the first pass gate, a second inverter whose output node receives the BLB through the second pass gate, a first instrument coupled between the output node of the first inverter and an input node of the second inverter, and a second instrument coupled between the output node of the second inverter and an input node of the first inverter, wherein the first and second instruments increase voltage discharge time of the memory cell when voltages at the output nodes of the inverters accidentally discharge.

摘要翻译： 公开了一种用于降低软错误率的存储单元及其形成方法。 存储单元包括第一位线信号（BL），与第一位线信号（BLB）互补的第二位线信号，耦合到BL的第一通道栅极，耦合到BLB的第二通道栅极，第一反相器 其输出节点通过第一传递门接收BL;输出节点通过第二传递门接收BLB的第二反相器，耦合在第一反相器的输出节点与第二反相器的输入节点之间的第一仪器， 第二仪器耦合在第二反相器的输出节点和第一反相器的输入节点之间，其中当逆变器的输出节点处的电压意外放电时，第一和第二仪器增加存储单元的电压放电时间。

公开(公告)号：US20050233223A1

公开(公告)日：2005-10-20

申请号：US10823822

申请日：2004-04-15

申请人： Jhon Liaw

发明人： Jhon Liaw

IPC分类号： G03C5/00 ,  G03F1/14 ,  G03F7/00 ,  G03F9/00 ,  H01L21/027 ,  H01L21/66

CPC分类号： G03F1/36

摘要： A method is disclosed for conducting optical proximity correction (OPC) on at least two features in a circuit design. After detecting a first feature having at least one end thereof to be in the proximity of one end of a second feature, a first OPC pattern is incorporated to the end of the first feature toward a first direction; and a second OPC pattern is incorporated to the end of the second feature toward a second direction that is substantially opposite from the first direction.

摘要翻译： 公开了一种用于在电路设计中的至少两个特征上进行光学邻近校正（OPC）的方法。 在检测到其第一特征的至少一端处于第二特征的一端附近之后，将第一OPC图案朝向第一方向结合到第一特征的端部; 并且第二OPC图案被结合到第二特征的端部朝向与第一方向基本相反的第二方向。

公开(公告)号：US20050224877A1

公开(公告)日：2005-10-13

申请号：US10815201

申请日：2004-03-31

申请人： Jhon Liaw

发明人： Jhon Liaw

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/01 ,  H01L27/02 ,  H01L27/11 ,  H01L27/12

CPC分类号： H01L27/1108 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1203

摘要： A semiconductor contact connection structure and the method for forming the same are disclosed. The connection structure has a first semiconductor device formed on an insulator substrate. A non-conducting gate interconnect layer is formed on the insulator substrate for connecting to a gate of a second semiconductor device, and a silicide layer formed on the gate interconnect layer and an active region of the first semiconductor device for making a connection thereof.

摘要翻译： 公开了一种半导体接触连接结构及其形成方法。 连接结构具有形成在绝缘体基板上的第一半导体器件。 在绝缘体基板上形成非导电栅极互连层，用于连接到第二半导体器件的栅极，以及形成在栅极互连层上的硅化物层和用于连接第一半导体器件的第一半导体器件的有源区。

公开(公告)号：US20060094171A1

公开(公告)日：2006-05-04

申请号：US10982456

申请日：2004-11-04

申请人： Jhon Liaw

发明人： Jhon Liaw

IPC分类号： H01L21/76 ,  H01L21/336

CPC分类号： H01L21/324 ,  H01L21/3247 ,  H01L21/76283 ,  H01L29/66575

摘要： A method for fabricating a semiconductor product employs a semiconductor substrate other than a bulk silicon semiconductor substrate. The semiconductor substrate is etched to form an etched semiconductor substrate having an isolation trench adjoining an active region. The etched semiconductor substrate is thermally annealed prior to forming a semiconductor device within the active region.

摘要翻译： 制造半导体产品的方法采用除体硅半导体衬底之外的半导体衬底。 蚀刻半导体衬底以形成具有邻接有源区的隔离沟槽的蚀刻半导体衬底。 蚀刻后的半导体衬底在有源区内形成半导体器件之前被热退火。

公开(公告)号：US20060006440A1

公开(公告)日：2006-01-12

申请号：US10886215

申请日：2004-07-06

申请人： Jhon Liaw

发明人： Jhon Liaw

IPC分类号： H01L27/108

CPC分类号： H01L21/28035 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4916 ,  Y10S257/903

摘要： An integrated circuit is disclosed having one or more devices having substantially similar physical gate electric thicknesses but different electrical gate electric thicknesses for accommodating various operation needs. One or more devices are manufactured with a same mask set using multiple doping processes to generate substantially similar physical gate dielectric thicknesses, but with different electrical gate dielectric thicknesses. The device undergoing multiple doping processes have different dopant concentrations, thereby providing different electrical characteristics such as the threshold voltages.

公开(公告)号：US20050260815A1

公开(公告)日：2005-11-24

申请号：US10851872

申请日：2004-05-21

申请人： Jhon Liaw

发明人： Jhon Liaw

IPC分类号： H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/10 ,  H01L29/772 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC分类号： H01L21/823842 ,  H01L21/28176 ,  H01L21/82385

摘要： A method is disclosed for forming at least two semiconductor devices with different gate electrode thicknesses. After forming a gate dielectric region, and determining whether a first or second device formed on the gate dielectric region expects a relatively faster gate dopant diffusion rate, a gate electrode layer is formed on the gate dielectric region wherein the gate electrode layer has a step-structure in which a portion thereof for the first device has a relatively larger thickness than that for the second device if the first device has a relatively faster gate dopant diffusion rate.

摘要翻译： 公开了用于形成具有不同栅电极厚度的至少两个半导体器件的方法。 在形成栅极电介质区域之后，并且确定形成在栅极介电区域上的第一或第二器件是否期望相对更快的栅极掺杂剂扩散速率，在栅极电介质区域上形成栅极电极层，其中栅极电极层具有阶跃 - 如果第一器件具有相对较快的栅极掺杂剂扩散速率，则第一器件的其一部分具有比第二器件的厚度更大的厚度的结构。