公开(公告)号：US5672538A

公开(公告)日：1997-09-30

申请号：US567015

申请日：1995-12-04

申请人： Jhon-Jhy Liaw ,  Jin-Yuan Lee ,  Sou-Wein Kuo

发明人： Jhon-Jhy Liaw ,  Jin-Yuan Lee ,  Sou-Wein Kuo

IPC分类号： H01L21/3105 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/31053 ,  H01L21/76202 ,  Y10S438/978

摘要： A method for improving the surface topology silicon wafers during the fabrication of integrated circuits is described. Regions of silicon oxide isolation, incorporated into the silicon surface by thermal oxidation, frequently present an undesirable surface topology consisting of raised regions around their perimeter. These protrusions undermine the integrity of metallization lines subsequently deposited over them. Specifically, the metal lines tend to be thinner over the surface protrusions and consequently incur high failure rates. After the isolation regions are incorporated, a silicon oxide layer is deposited which is then etched back using a unidirectional anisotropic etching step which leaves behind portions of the layer in the regions of the steepest surface gradients. This results in smoothing out the irregularities and consequently provides for more uniform and reliable metallization lines.

摘要翻译： 描述了在集成电路制造期间改进表面拓扑硅晶片的方法。 通过热氧化并入硅​​表面的氧化硅隔离区域经常呈现出不期望的表面拓扑结构，其周围包括凸起区域。 这些突起破坏随后沉积在其上的金属化线的完整性。 具体来说，金属线在表面突起上倾向于更薄，因此导致高故障率。 在并入隔离区之后，沉积氧化硅层，然后使用单向各向异性蚀刻步骤将其回蚀刻，该步骤在最陡的表面梯度的区域中留下该层的部分。 这导致平滑不规则性，并因此提供更均匀和可靠的金属化线。

公开(公告)号：US5998249A

公开(公告)日：1999-12-07

申请号：US86822

申请日：1998-05-29

申请人： Jhon-Jhy Liaw ,  Jin-Yuan Lee

发明人： Jhon-Jhy Liaw ,  Jin-Yuan Lee

IPC分类号： H01L21/8244

CPC分类号： H01L27/11 ,  Y10S148/02

摘要： A method for forming an SRAM cell, on a semiconductor substrate, comprised of MOSFET devices, and polysilicon load resistors, has been developed. The process for forming the SRAM cell features the use of two, self-aligned contact, (SAC), structures, a polycide SAC structure, used for contact to a source region of a MOSFET pull down transistor, and a tungsten SAC structure, used for contact to a source region of a MOSFET pass gate transistor. A buried contact region is also featured in this SRAM design and fabrication procedure, used to connect underlying active device regions, of MOSFET pull down transistors, and MOSFET pass gate transistors.

摘要翻译： 已经开发了用于形成由MOSFET器件和多晶硅负载电阻器构成的半导体衬底上的SRAM单元的方法。 用于形成SRAM单元的工艺特征在于使用两个自对准接触（SAC），结构，用于与MOSFET下拉晶体管的源极区域接触的多晶硅SAC结构，以及钨SAC结构 用于与MOSFET栅极晶体管的源极区域接触。 这种SRAM设计和制造过程中还涉及一个埋置接触区域，用于连接底层有源器件区域，MOSFET下拉晶体管和MOSFET栅极晶体管。

公开(公告)号：US5926706A

公开(公告)日：1999-07-20

申请号：US835578

申请日：1997-04-09

申请人： Jhon-Jhy Liaw ,  Jin-Yuan Lee

发明人： Jhon-Jhy Liaw ,  Jin-Yuan Lee

IPC分类号： H01L21/265 ,  H01L21/285 ,  H01L21/8244 ,  H01L27/11

CPC分类号： H01L27/11 ,  H01L21/28512 ,  H01L21/26586

摘要： A method is achieved for forming buried contacts with diffused contact regions on semiconductor integrated circuits having low sheet resistance between the buried contacts and the field effect transistors. The method also allows for greater misalignment tolerances that prevent trenching or electrical opens from occurring in the diffused contact regions when etching the polycide interconnecting lines over the contacts. The method utilizes the etch back of an opening in the photoresist contact mask and a subsequent angular implant to extend the diffused contact regions to reduce the sheet resistance between the buried contacts and the FETs. The method is especially useful for electrically connecting the drain of the pass transistor to the gate of the pull-down transistor on static RAM devices.

摘要翻译： 实现了在掩埋触点和场效应晶体管之间具有低薄层电阻的半导体集成电路上形成具有扩散接触区域的掩埋触点的方法。 该方法还允许更大的未对准公差，其当在触点上蚀刻多晶硅互连线时，防止在扩散接触区域中发生开沟或电开路。 该方法利用光致抗蚀剂接触掩模中的开口的蚀刻背面和随后的角度注入来延伸扩散接触区域，以减小掩埋触点和FET之间的薄层电阻。 该方法特别适用于将静态RAM器件中的传输晶体管的漏极电连接到下拉晶体管的栅极。

公开(公告)号：US06214698B1

公开(公告)日：2001-04-10

申请号：US09480270

申请日：2000-01-11

申请人： Jhon-Jhy Liaw ,  Jin-Yuan Lee ,  Kuei-Ying Lee ,  Chu-Yun Fu ,  Kong-Beng Thei

发明人： Jhon-Jhy Liaw ,  Jin-Yuan Lee ,  Kuei-Ying Lee ,  Chu-Yun Fu ,  Kong-Beng Thei

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： A method for filling a trench within a substrate. First a substrate is provided having a trench formed therein. The trench has a bottom surface and opposing side walls. An undoped silicon glass liner is then thermally grown to coat the bottom surface and side walls of the trench. An undoped silicon oxide layer is then deposited over the undoped silicon glass liner. A boron doped silicon oxide layer is then deposited over the undoped silicon oxide layer, filling the trench. The boron doped silicon oxide layer is then heated to reflow the boron doped silicon oxide to fill any void initially formed within the boron doped silicon oxide layer within the trench, thereby eliminating any void so formed.

摘要翻译： 一种填充衬底内的沟槽的方法。 首先，提供具有形成在其中的沟槽的衬底。 沟槽具有底面和相对的侧壁。 然后将未掺杂的硅玻璃衬里热生长以涂覆沟槽的底表面和侧壁。 然后将未掺杂的氧化硅层沉积在未掺杂的硅玻璃衬垫上。 然后将硼掺杂的氧化硅层沉积在未掺杂的氧化硅层上，填充沟槽。 然后加热硼掺杂的氧化硅层以回流硼掺杂的氧化硅以填充初始形成在沟槽内的硼掺杂的氧化硅层内的任何空隙，从而消除如此形成的任何空隙。

公开(公告)号：US5960276A

公开(公告)日：1999-09-28

申请号：US161406

申请日：1998-09-28

申请人： Jhon-Jhy Liaw ,  Dun-Nian Yaung ,  Jin-Yuan Lee

发明人： Jhon-Jhy Liaw ,  Dun-Nian Yaung ,  Jin-Yuan Lee

IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L21/76

CPC分类号： H01L21/76229 ,  H01L21/76232 ,  H01L21/76237 ,  H01L21/823878

摘要： A method to form, in a NMOS area, a shallow trench isolation (STI) having B doped sidewalls regions 44 to reduce the NMOS reverse narrow width effect in narrow active areas 12N (e.g., narrow channel regions

摘要翻译： 在NMOS区域中形成具有B掺杂侧壁区域44的浅沟槽隔离（STI）以减小窄有源区12N（例如窄通道区域<0.1μm宽）中的NMOS反向窄宽度效应的方法。 提供具有NMOS区域13和PMOS区域15的衬底。衬底氧化物层20和阻挡层22形成在衬底上。 沟槽24在NMOS和PMOS区域中的衬底10中蚀刻。 蚀刻形成窄的有源区域12N和宽的有源区域12W。 狭窄的有源区域12N具有在0.4和1.0μm之间的宽度。 在衬底上的沟槽的侧壁和底部上生长衬里层30。 形成第一光致抗蚀剂层，覆盖PMOS区域并且在NMOS区域上具有第一开口。 在关键步骤中，在衬底中形成硼掺杂区域44的沟槽的侧壁和底部中进行大角度硼注入。 去除第一光致抗蚀剂层。 绝缘层50形成在NMOS和PMOS区域的沟槽中。 PMOS区域中的PMOS场效应晶体管和NMOS区域中的NMOS场效应晶体管形成。 本发明的硼掺杂区域44减小了NMOS区域中的反向窄的宽效应。

公开(公告)号：US5872063A

公开(公告)日：1999-02-16

申请号：US5568

申请日：1998-01-12

申请人： Li-chih Chao ,  Jhon-Jhy Liaw ,  Yuan-Chang Huang ,  Jin-Yuan Lee

发明人： Li-chih Chao ,  Jhon-Jhy Liaw ,  Yuan-Chang Huang ,  Jin-Yuan Lee

IPC分类号： H01L21/311 ,  H01L21/60 ,  H01L21/70

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  Y10S257/90

摘要： A self-aligned structure and method of etching contact holes in the self-aligned structure are described. The dielectric materials, etching methods, and etchants are chosen to provide high selectivity etching. The structure comprises an electrode with a silicon oxy-nitride cap and silicon oxy-nitride spacers on the sidewalls of the electrode and the cap. An etch stop layer of silicon nitride is deposited over the substrate covering the spacers and cap. A layer of silicon oxide is deposited over the etch stop layer. Etching methods and etchants are used which provide a ratio of the etching rate of silicon oxide to the etching rate of silicon nitride or silicon oxy-nitride of at least eight and a ratio of the etching rate of silicon nitride to the etching rate of silicon oxy-nitride of at least two.

摘要翻译： 描述了自对准结构和蚀刻自对准结构中的接触孔的方法。 选择介电材料，蚀刻方法和蚀刻剂以提供高选择性蚀刻。 该结构包括在电极和盖的侧壁上具有氮氧化硅帽和氮氧化硅间隔物的电极。 氮化硅的蚀刻停止层沉积在覆盖间隔物和盖的衬底上。 氧化硅层沉积在蚀刻停止层上。 使用蚀刻方法和蚀刻剂，其提供氧化硅的蚀刻速率与氮化硅或氮氧化硅的蚀刻速率的比率至少为8，氮化硅的蚀刻速率与硅氧化物的蚀刻速率的比率 至少两个。

公开(公告)号：US5866449A

公开(公告)日：1999-02-02

申请号：US958426

申请日：1997-10-27

申请人： Jhon-Jhy Liaw ,  Jin-Yuan Lee

发明人： Jhon-Jhy Liaw ,  Jin-Yuan Lee

IPC分类号： H01L21/8244 ,  H01L27/11

CPC分类号： H01L27/11 ,  H01L27/1112 ,  Y10S257/903

摘要： This is a method of forming an SRAM transistor cell on a well in a doped semiconductor substrate. Form a gate oxide layer and a split gate layer with buried contact regions in the well and openings through the split gate layer and the gate oxide layer to the well. Form an intermediate conductor layer and a hard silicon oxide mask layer and define gate conductors. Form lightly doped source/drain regions, form spacers and source/drain regions in the well. Form a first inter-conductor dielectric layer on the cell. Define a self-aligned contact region in the cell above source/drain regions. Form a second conductor layer over the cell and patterning the second conductor layer to form a via in the self-aligned contact region. Form a second inter-conductor dielectric layer on the cell, a third conductor layer over the cell and patterning the third conductor layer to form a first resistor connected to the self-aligned contact region.

摘要翻译： 这是在掺杂半导体衬底中的阱上形成SRAM晶体管单元的方法。 在阱中形成具有掩埋接触区域的栅极氧化物层和分离栅极层，并且通过分裂栅极层和栅极氧化物层到达阱的开口。 形成中间导体层和硬氧化硅掩模层，并限定栅极导体。 形成轻掺杂的源极/漏极区域，在阱中形成间隔物和源极/漏极区域。 在电池上形成第一个导体间介质层。 在源极/漏极区域之上的单元格中定义自对准接触区域。 在单元上方形成第二导体层并且图案化第二导体层以在自对准接触区域中形成通孔。 在单元上形成第二导体间介质层，在单元上方形成第三导体层，并构图第三导体层，以形成连接到自对准接触区的第一电阻。

公开(公告)号：US06172411B2

公开(公告)日：2001-01-09

申请号：US09208921

申请日：1998-12-10

申请人： Li-chih Chao ,  Jhon-Jhy Liaw ,  Yuan-Chang Huang ,  Jin-Yuan Lee

发明人： Li-chih Chao ,  Jhon-Jhy Liaw ,  Yuan-Chang Huang ,  Jin-Yuan Lee

IPC分类号： H01L27088

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  Y10S257/90

摘要： A self-aligned structure and method of etching contact holes in the self-aligned structure are described. The dielectric materials, etching methods, and etchants are chosen to provide high selectivity etching. The structure comprises an electrode with a silicon oxy-nitride cap and silicon oxy-nitride spacers on the sidewalls of the electrode and the cap. An etch stop layer of silicon nitride is deposited over the substrate covering the spacers and cap. A layer of silicon oxide is deposited over the etch stop layer. Etching methods and etchants are used which provide a ratio of the etching rate of silicon oxide to the etching rate of silicon nitride or silicon oxy-nitride of at least eight and a ratio of the etching rate of silicon nitride to the etching rate of silicon oxy-nitride of at least two.

摘要翻译： 描述了自对准结构和蚀刻自对准结构中的接触孔的方法。 选择介电材料，蚀刻方法和蚀刻剂以提供高选择性蚀刻。 该结构包括在电极和盖的侧壁上具有氮氧化硅帽和氮氧化硅间隔物的电极。 氮化硅的蚀刻停止层沉积在覆盖间隔物和盖的衬底上。 氧化硅层沉积在蚀刻停止层上。 使用蚀刻方法和蚀刻剂，其提供氧化硅的蚀刻速率与氮化硅或氮氧化硅的蚀刻速率的比率至少为8，氮化硅的蚀刻速率与硅氧化物的蚀刻速率的比率 至少两个。

公开(公告)号：US5915192A

公开(公告)日：1999-06-22

申请号：US928280

申请日：1997-09-12

申请人： Jhon-Jhy Liaw ,  Jin-Yuan Lee

发明人： Jhon-Jhy Liaw ,  Jin-Yuan Lee

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232 ,  Y10S148/05

摘要： A method of forming a trench isolation is disclosed. The initial step includes forming a first dielectric layer on a substrate of a transistor followed by a second dielectric layer formed on the first dielectric layer. Next, the substrate, the first dielectric layer and the second dielectric layer is patterned and etched to form a trench in the substrate, the first dielectric layer and the second dielectric layer. Next, a third dielectric layer is formed on the surface of the side wall of the trench followed by isotropically etching the bottom of the trench. Finally, a fourth dielectric layer on the surface of the trench is formed and the trench is filled with a dielectric material.

摘要翻译： 公开了形成沟槽隔离的方法。 初始步骤包括在晶体管的衬底上形成第一电介质层，随后形成在第一介电层上的第二电介质层。 接下来，对衬底，第一电介质层和第二电介质层进行构图和蚀刻，以在衬底，第一介电层和第二电介质层中形成沟槽。 接下来，在沟槽的侧壁的表面上形成第三电介质层，然后各向同性蚀刻沟槽的底部。 最后，形成沟槽表面上的第四电介质层，并用电介质材料填充沟槽。

公开(公告)号：US5554565A

公开(公告)日：1996-09-10

申请号：US606832

申请日：1996-02-26

申请人： Jhon-Jhy Liaw ,  Jin-Yuan Lee ,  Ming-Chang Teng

发明人： Jhon-Jhy Liaw ,  Jin-Yuan Lee ,  Ming-Chang Teng

IPC分类号： H01L21/768 ,  H01L21/441

CPC分类号： H01L21/76855 ,  H01L21/76801 ,  H01L21/76814 ,  H01L21/76877

摘要： An improved method for the fabrication of an ohmic, low resistance contact to heavily doped silicon is described using a CVD deposited tungsten plug provided with Ti/TiN barrier metallurgy. The method provides for surface planarizatiion by depositing first a layer of silicon oxide followed by a layer of borophosphosilicate glass onto a silicon wafer containing integrated circuit devices. After the glass is thermally flowed to planarize its surface, it is etched back to a suitable thickness and a second layer of silicon oxide is deposited over the now-planar surface. Contact holes are patterned in the composite silicon oxide-glass-silicon oxide structure and the exposed silicon device contacts are ion-implanted. The implant is then activated by rapid-thermal-annealing. The presence of the second silicon oxide layer prevents the upper corners of the contact openings from flowing and encroaching into the opening as would occur in its absence. Not only does this provide for void-free filling of the contact openings by the tungsten contact deposition but it also permits the use of higher temperatures for the implant anneal.

摘要翻译： 使用具有Ti / TiN屏蔽冶金的CVD沉积钨插塞来描述用于制造对重掺杂硅的欧姆低电阻接触的改进方法。 该方法通过首先沉积氧化硅层，然后通过一层硼磷硅酸盐玻璃沉积到含有集成电路器件的硅晶片上来提供表面平坦化。 在玻璃被热流动以使其表面平坦化之后，将其回蚀刻到合适的厚度，并且在现在的平面表面上沉积第二层氧化硅。 在复合氧化硅 - 玻璃 - 氧化硅结构中图案化接触孔，并且暴露的硅器件触点被离子注入。 然后通过快速热退火激活植入物。 第二氧化硅层的存在防止接触开口的上角流动并侵入开口，如在其不存在时将发生的那样。 这不仅提供了通过钨接触沉积的无孔填充接触开口，而且还允许使用较高的温度进行注入退火。