公开(公告)号：US20110279298A1

公开(公告)日：2011-11-17

申请号：US13100596

申请日：2011-05-04

申请人： Ji-Hun KIM ,  Yeong-Joon Son ,  Joon-Ho Na ,  Jeong-Yeol Bae ,  Sang-Gug Lee

发明人： Ji-Hun KIM ,  Yeong-Joon Son ,  Joon-Ho Na ,  Jeong-Yeol Bae ,  Sang-Gug Lee

IPC分类号： H03M1/66

CPC分类号： H03M1/68 ,  H03M1/765 ,  H03M1/804

摘要： A DAC circuit using a charge subtraction method and a change transfer interpolation method includes resistor cells configured to divide a voltage of data of total K bits (=upper M bits+lower N bits) by resistance dividers; a decoder group configured to receive digital data of the M bits and the N bits divided in the resistor cells, process the digital data by the unit of 2 bits, and output respective corresponding voltages; a capacitor group configured to receive the voltages outputted from the decoder group and realize charge charging by a charge subtraction method and charge transferring by a charge transfer interpolation method; and an operational amplifier having a first input terminal which receives a reference voltage and a second input terminal which receives an interpolation voltage corresponding to an amount of charges transferred from the capacitor group, and configured to generate an output voltage.

摘要翻译： 使用电荷减法和变迁内插法的DAC电路包括电阻单元，其被配置为通过电阻分压器来分配总共K位（=高M位+低N位）的数据的电压; 配置为接收M位的数字数据和在电阻单元中划分的N位的解码器组，以2位为单位处理数字数据，并输出相应的对应电压; 电容器组，被配置为接收从解码器组输出的电压，并通过电荷减法方法实现充电充电，并通过电荷转移插值方法进行电荷转移; 以及运算放大器，其具有接收参考电压的第一输入端子和接收与从所述电容器组传送的电荷量对应的内插电压的第二输入端子，并且被配置为产生输出电压。

公开(公告)号：US20110279407A1

公开(公告)日：2011-11-17

申请号：US13105301

申请日：2011-05-11

申请人： Ji-Hun KIM ,  Young-Bok Kim ,  Joon-Ho Na ,  Yeong-Shin Jang ,  Sang-Gug Lee

发明人： Ji-Hun KIM ,  Young-Bok Kim ,  Joon-Ho Na ,  Yeong-Shin Jang ,  Sang-Gug Lee

IPC分类号： G06F3/044

CPC分类号： G06F3/044 ,  G01R27/2605

摘要： A circuit for processing a touch line signal of a touch screen includes a plurality of sensing read circuits and a switch unit. The plurality of sensing read circuits include sensing read-out units and integrators, respectively. The sensing read-out units are configured to precharge a first sensor capacitor and a second sensor capacitor formed on a touch screen panel with a ground voltage and a supply voltage, allow charges charged in the first sensor capacitor and the second sensor capacitor to be shared, and read-out a charge sharing result obtained by allowing the charges of the first sensor capacitor and the second sensor capacitor to be shared. The integrators are configured to integrate output voltages of the sensing read-out units. The switch unit is configured to sequentially connect output terminals of the plurality of sensing read circuits to an input terminal of an analog-to-digital converter.

摘要翻译： 用于处理触摸屏的触摸线信号的电路包括多个感测读取电路和开关单元。 多个感测读取电路分别包括感测读出单元和积分器。 感测读出单元被配置为对接地电压和电源电压在触摸屏面板上形成的第一传感器电容器和第二传感器电容器进行预充电，允许在第一传感器电容器和第二传感器电容器中充电的电荷被共享 并且读出通过允许共享第一传感器电容器和第二传感器电容器的电荷而获得的电荷共享结果。 集成器被配置为集成感测读出单元的输出电压。 开关单元被配置为将多个感测读取电路的输出端子顺序地连接到模数转换器的输入端子。

公开(公告)号：US08659323B2

公开(公告)日：2014-02-25

申请号：US13250037

申请日：2011-09-30

申请人： Sang-Gug Lee ,  Seungjin Kim

发明人： Sang-Gug Lee ,  Seungjin Kim

IPC分类号： H03B21/00

CPC分类号： H03L7/1976

摘要： A frequency synthesizer includes: a delta sigma modulator that outputs an input value to a sequentially changing digital value; an analog path unit that converts the digital value to an analog value according to a first conversion gain; an accumulator that accumulates a difference between the input and digital values; a digital to analog converter (DAC) that compensates an output value of the accumulator according to a second conversion gain; a correction loop that extracts analog tendency by adding an output of the analog path unit and an output of the DAC and that extracts digital tendency from an output of the accumulator and adjusts the second conversion gain by comparing the analog and digital tendency; and a voltage control oscillator that generates an output frequency by adding an output of the analog path unit and an output according to an adjusted second conversion gain of the DAC.

摘要翻译： 频率合成器包括：ΔΣ调制器，其将输入值输出到顺序变化的数字值; 模拟路径单元，其根据第一转换增益将数字值转换为模拟值; 累加器，其累积输入和数字值之间的差; 数模转换器（DAC），其根据第二转换增益来补偿所述累加器的输出值; 校正循环，通过添加模拟路径单元的输出和DAC的输出来提取模拟趋势，并且从累加器的输出提取数字趋势，并通过比较模拟和数字趋势来调整第二转换增益; 以及电压控制振荡器，其通过将所述模拟路径单元的输出和根据所述DAC的经调整的第二转换增益的输出相加来产生输出频率。

公开(公告)号：US20070173218A1

公开(公告)日：2007-07-26

申请号：US11409886

申请日：2006-04-24

申请人： Nam-Jin Oh ,  Sang-Gug Lee

发明人： Nam-Jin Oh ,  Sang-Gug Lee

IPC分类号： H04B7/00

CPC分类号： H03B27/00 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243

摘要： A local oscillator without a frequency divider is provided. The local oscillator includes a quadrature voltage controlled oscillator generating I and Q signals having a frequency which is one-third of a local oscillation frequency, and a differential second-harmonic signal having a frequency which is two-thirds of the local oscillation frequency, a poly-phase filter converting the differential second-harmonic signal input from the quadrature voltage controlled oscillator into I and Q signals, and a single side band (SSB) mixer receiving the I and Q signals having the frequency which is one-third of the local oscillation frequency from the quadrature voltage controlled oscillator as an input and receiving the I and Q signals having the frequency which is two-thirds of the local oscillation frequency from the poly-phase filter as an input, and outputting the I and Q signals having the local oscillation frequency.

摘要翻译： 提供了没有分频器的本地振荡器。 本地振荡器包括正交压控振荡器，其生成具有本地振荡频率的三分之一的频率的I和Q信号，以及具有作为本地振荡频率的三分之二的频率的差分二次谐波信号， 将从正交压控振荡器输入的差分二次谐波信号转换为I和Q信号的多相滤波器以及接收具有本地的三分之一频率的I和Q信号的单边带（SSB）混频器 振荡频率作为输入，从作为输入的多相滤波器接收具有作为本地振荡频率的三分之二的频率的I和Q信号，并输出具有 本地振荡频率。

公开(公告)号：US5686822A

公开(公告)日：1997-11-11

申请号：US640108

申请日：1996-04-30

申请人： Gregg Douglas Croft ,  Sang-Gug Lee ,  Steven Robert Jost

发明人： Gregg Douglas Croft ,  Sang-Gug Lee ,  Steven Robert Jost

IPC分类号： G05F3/26 ,  G05F1/10

CPC分类号： G05F3/265

摘要： A current generator and method of making a current generator in which two resistors are provided, each in series with one of two transistors in the generator, and in which one of the resistors is trimmed if the reference current is too large and the other is trimmed if the reference current is too small, thereby obviating the problems of the prior art in which one resistor must be trimmed by a potentially large and unacceptable amount. The two resistors are formed with a distribution of resistances which is centered on their corresponding target resistance values so that the number of resistors to be trimmed and the amount of trimming per resistor are reduced. The appropriate target resistances of the resistors can be determined if a maximum trim factor is set. The method is insensitive to variations in the process by which the resistances of the resistors are initially set and reduces the variability of the untrimmed reference current with respect to resistor critical dimensions.

摘要翻译： 一种电流发生器和制造电流发生器的方法，其中设置有两个电阻器，每个电阻器与发生器中的两个晶体管中的一个串联，并且如果参考电流太大而另一个被修整，则电阻器中的一个被修整 如果参考电流太小，从而避免了现有技术的问题，其中一个电阻器必须用可能大的和不可接受的量来修整。 两个电阻器形成有以其对应的目标电阻值为中心的电阻分布，使得要修整的电阻器的数量和每个电阻器的修整量减少。 如果设置了最大微调因子，则可以确定电阻器的适当目标电阻。 该方法对于最初设置电阻器的电阻的过程中的变化不敏感，并且减小未匹配参考电流相对于电阻器关键尺寸的可变性。

公开(公告)号：US20120306542A1

公开(公告)日：2012-12-06

申请号：US13250037

申请日：2011-09-30

申请人： Sang-Gug Lee ,  Seungjin Kim

发明人： Sang-Gug Lee ,  Seungjin Kim

IPC分类号： H03B21/00

CPC分类号： H03L7/1976

摘要： A frequency synthesizer includes: a delta sigma modulator that outputs an input value to a sequentially changing digital value; an analog path unit that converts the digital value to an analog value according to a first conversion gain; an accumulator that accumulates a difference between the input and digital values; a digital to analog converter (DAC) that compensates an output value of the accumulator according to a second conversion gain; a correction loop that extracts analog tendency by adding an output of the analog path unit and an output of the DAC and that extracts digital tendency from an output of the accumulator and adjusts the second conversion gain by comparing the analog and digital tendency; and a voltage control oscillator that generates an output frequency by adding an output of the analog path unit and an output according to an adjusted second conversion gain of the DAC.

摘要翻译： 频率合成器包括：ΔΣ调制器，其将输入值输出到顺序变化的数字值; 模拟路径单元，其根据第一转换增益将数字值转换为模拟值; 累加器，其累积输入和数字值之间的差; 数模转换器（DAC），其根据第二转换增益补偿所述累加器的输出值; 校正循环，通过添加模拟路径单元的输出和DAC的输出来提取模拟趋势，并且从累加器的输出提取数字趋势，并通过比较模拟和数字趋势来调整第二转换增益; 以及电压控制振荡器，其通过将所述模拟路径单元的输出和根据所述DAC的经调整的第二转换增益的输出相加来产生输出频率。

公开(公告)号：US08106718B2

公开(公告)日：2012-01-31

申请号：US12690136

申请日：2010-01-20

申请人： Sang-Gug Lee ,  Jong-Phil Hong

发明人： Sang-Gug Lee ,  Jong-Phil Hong

IPC分类号： H03B5/08

CPC分类号： H03B5/1228 ,  H03B5/1215 ,  H03B5/1243 ,  H03B5/1271

摘要： A voltage controlled oscillator outputting a differential signal includes: an inductor connected to a first power supply supplying first voltage; first and second transistors for differential switching; first and second variable capacitors connected to the inductor in parallel; a third transistor of which a gate electrode is connected to a first node; and a fourth transistor of which a gate electrode is connected to a second node. When bias voltage is applied to the gate electrode of the first transistor to be turned on, negative resistance is generated by voltage applied to the first capacitor and the second capacitor through the first transistor. When voltage outputted through the first node is applied to the gate electrode of the third transistor to be turned on, the voltage is additionally applied to the first capacitor and the second capacitor by the third transistor to increase the negative resistance.

摘要翻译： 输出差分信号的压控振荡器包括：电感器，连接到提供第一电压的第一电源; 用于差分开关的第一和第二晶体管; 并联连接到电感器的第一和第二可变电容器; 栅电极连接到第一节点的第三晶体管; 以及栅电极连接到第二节点的第四晶体管。 当偏置电压施加到要导通的第一晶体管的栅电极时，通过第一晶体管施加到第一电容器和第二电容器的电压产生负电阻。 当通过第一节点输出的电压被施加到要导通的第三晶体管的栅电极时，由第三晶体管将电压附加到第一电容器和第二电容器以增加负电阻。

公开(公告)号：US20060055477A1

公开(公告)日：2006-03-16

申请号：US10941585

申请日：2004-09-15

申请人： Dong Kang ,  Choong-yul Cha ,  Sang-Gug Lee

发明人： Dong Kang ,  Choong-yul Cha ,  Sang-Gug Lee

IPC分类号： H03B5/12

CPC分类号： H03B5/1228 ,  H03B5/1218 ,  H03B5/1243

摘要： A voltage controlled oscillator is provided. The oscillator has an oscillator amplifier core formed of a complementary pair of FETs connected with their gates in common and connected to share a bias current. An inductance is connected between the common gates and the common drains of the FETs. The inductance may be an inductor element or an inductance of a physical structure of the circuit, such as a bond wire. The voltage controlled oscillator includes a variable capacitor stage connected at the input of the oscillator amplifier stage and a buffer amplifier stage connected at the output of the oscillator amplifier stage. The buffer amplifier of one embodiment includes a pair of complementary FETs having common gates connected to the common drains of the FETs of the oscillator amplifier stage. The buffer amplifier stage also include an inductor and a capacitor connected between common drains of the buffer amplifier FETs and the output.

摘要翻译： 提供压控振荡器。 该振荡器具有振荡器放大器芯，其由互补的一对FET形成，与它们的栅极共同连接并连接以共享偏置电流。 电感连接在公共栅极和FET的公共漏极之间。 电感可以是电感器元件或电路的物理结构的电感，例如接合线。 压控振荡器包括连接在振荡器放大器级的输入端的可变电容器级和连接在振荡器放大器级的输出端的缓冲放大器级。 一个实施例的缓冲放大器包括一对互补FET，其具有连接到振荡器放大器级的FET的公共漏极的公共栅极。 缓冲放大器级还包括电感器和连接在缓冲放大器FET的公共漏极和输出端之间的电容器。

公开(公告)号：US5809410A

公开(公告)日：1998-09-15

申请号：US90617

申请日：1993-07-12

申请人： Carlton Stuebing ,  Richard Douglas Schultz ,  Thomas David Brogan ,  Sang-Gug Lee

发明人： Carlton Stuebing ,  Richard Douglas Schultz ,  Thomas David Brogan ,  Sang-Gug Lee

IPC分类号： H03D7/14 ,  H03F1/30 ,  H03F3/19 ,  H03F3/45 ,  H04B1/28

CPC分类号： H03F3/45089 ,  H03D7/1433 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1491 ,  H03F1/302 ,  H03D2200/0025 ,  H03D2200/0043 ,  H03F2200/453 ,  H03F2203/45311 ,  H03F2203/45374 ,  H03F2203/45464 ,  H03F2203/45508 ,  H03F2203/45544 ,  H03F2203/45596 ,  H03F2203/45702

摘要： A single bias block for a single or multiple low voltage RF circuits including one or more amplifiers and one or more single or double balanced mixers with compensation for temperature and integrated circuit process parameters. The power supply may be a lower voltage without sacrificing the dynamic range of the amplifier and/or mixer by applying full power supply voltage to the load with the bias applied to the base circuit through an operational amplifier and/or buffer circuit. For the mixer, a lower noise figure may also be realized by moving the gain control impedance from the emitter to the collector circuit. The circuits may be discrete components or part of an integrated circuit. Methods are disclosed for reducing the power supply voltage without affecting the dynamic range of an amplifier, for temperature and process parameter compensation, and for controlling the gain of a mixer without affecting input or output impedance.

公开(公告)号：US08688063B2

公开(公告)日：2014-04-01

申请号：US13423685

申请日：2012-03-19

申请人： Sang-Gug Lee ,  Yuna Shim

发明人： Sang-Gug Lee ,  Yuna Shim

IPC分类号： H04B1/18

CPC分类号： H03F3/45071 ,  H03F1/223 ,  H03F3/193 ,  H03F2200/294 ,  H04B1/006

摘要： A receiving apparatus in a wireless communication system includes: an antenna configured to receive a wireless frequency signal including a first frequency band signal and a second frequency band signal; a low noise amplifier (LNA) configured to amplify the wireless frequency signal, output the first frequency band signal as a differential phase signal, and output the second frequency band signal as a common phase signal; a differentiator configured to pass only the differential phase signal between the signals outputted from the LNA; and a combiner configured to pass only the common phase signal between the signals outputted from the LNA.

摘要翻译： 无线通信系统中的接收装置包括：天线，被配置为接收包括第一频带信号和第二频带信号的无线频率信号; 配置为放大无线频率信号的低噪声放大器（LNA），将第一频带信号输出为差分相位信号，并输出第二频带信号作为公共相位信号; 一个微分器，被配置为仅在所述LNA输出的信号之间通过所述差分相位信号; 以及组合器，其被配置为仅在从LNA输出的信号之间传递公共相位信号。