公开(公告)号：US20060240361A1

公开(公告)日：2006-10-26

申请号：US11407295

申请日：2006-04-20

申请人： Ji-young Lee ,  Joon-soo Park ,  Sang-gyun Woo

发明人： Ji-young Lee ,  Joon-soo Park ,  Sang-gyun Woo

IPC分类号： G03F7/26

CPC分类号： H01L21/0337 ,  H01L21/0338

摘要： A method of forming a small pitch pattern using double spacers is provided. A material layer and first hard masks are used and characterized by a line pattern having a smaller line width than a separation distance between adjacent mask elements. A first spacer layer covering sidewall portions of the first hard mask and a second spacer layer are formed, and spacer-etched, thereby forming a spacer pattern-shaped second hard mask on sidewall portions of the first hard mask. A portion of the second spacer layer between the first hard mask and the second hard mask is selectively removed. The material layer is selectively etched using the first and second hard masks as etch masks, thereby forming the small pitch pattern.

摘要翻译： 提供了使用双间隔物形成小间距图案的方法。 使用材料层和第一硬掩模，其特征在于具有比相邻掩模元件之间的间隔距离更小的线宽的线图案。 形成覆盖第一硬掩模和第二间隔层的侧壁部分的第一间隔层，并间隔蚀刻，从而在第一硬掩模的侧壁部分上形成间隔图案形状的第二硬掩模。 选择性地去除第一硬掩模和第二硬掩模之间的第二间隔层的一部分。 使用第一和第二硬掩模作为蚀刻掩模来选择性地蚀刻材料层，从而形成小间距图案。

公开(公告)号：US08062981B2

公开(公告)日：2011-11-22

申请号：US12327006

申请日：2008-12-03

申请人： Ji-young Lee ,  Sang-gyun Woo ,  Joon-soo Park

发明人： Ji-young Lee ,  Sang-gyun Woo ,  Joon-soo Park

IPC分类号： H01L21/302

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338

摘要： A method of forming a fine pattern of a semiconductor device using a fine pitch hard mask is provided. A first hard mask pattern including first line patterns formed on an etch target layer of a substrate with a first pitch is formed. A first layer including a top surface where a recess is formed between adjacent first line patterns is formed. A second hard mask pattern including second line patterns within the recess is formed. An anisotropic etching process is performed on the first layer using the first and the second line patterns as an etch mask. Another anisotropic etching process is performed on the etch target layer using the first and the second hard mask patterns as an etch mask.

摘要翻译： 提供了使用细间距硬掩模形成半导体器件的精细图案的方法。 形成包括形成在具有第一间距的基板的蚀刻目标层上的第一线图案的第一硬掩模图案。 形成包括在相邻的第一线图案之间形成有凹部的顶面的第一层。 形成包括凹部内的第二线图案的第二硬掩模图案。 使用第一和第二线图案作为蚀刻掩模在第一层上进行各向异性蚀刻处理。 使用第一和第二硬掩模图案作为蚀刻掩模在蚀刻目标层上执行另一种各向异性蚀刻工艺。

公开(公告)号：US07842601B2

公开(公告)日：2010-11-30

申请号：US11407295

申请日：2006-04-20

申请人： Ji-young Lee ,  Joon-soo Park ,  Sang-gyun Woo

发明人： Ji-young Lee ,  Joon-soo Park ,  Sang-gyun Woo

IPC分类号： H01L21/4763

CPC分类号： H01L21/0337 ,  H01L21/0338

摘要： A method of forming a small pitch pattern using double spacers is provided. A material layer and first hard masks are used and characterized by a line pattern having a smaller line width than a separation distance between adjacent mask elements. A first spacer layer covering sidewall portions of the first hard mask and a second spacer layer are formed, and spacer-etched, thereby forming a spacer pattern-shaped second hard mask on sidewall portions of the first hard mask. A portion of the first spacer layer between the first hard mask and the second hard mask is selectively removed. The material layer is selectively etched using the first and second hard masks as etch masks, thereby forming the small pitch pattern.

摘要翻译： 提供了使用双间隔物形成小间距图案的方法。 使用材料层和第一硬掩模，其特征在于具有比相邻掩模元件之间的间隔距离更小的线宽的线图案。 形成覆盖第一硬掩模和第二间隔层的侧壁部分的第一间隔层，并间隔蚀刻，从而在第一硬掩模的侧壁部分上形成间隔图案形状的第二硬掩模。 选择性地去除第一硬掩模和第二硬掩模之间的第一间隔层的一部分。 使用第一和第二硬掩模作为蚀刻掩模来选择性地蚀刻材料层，从而形成小间距图案。

公开(公告)号：US07473647B2

公开(公告)日：2009-01-06

申请号：US11367437

申请日：2006-03-06

申请人： Ji-young Lee ,  Sang-gyun Woo ,  Joon-soo Park

发明人： Ji-young Lee ,  Sang-gyun Woo ,  Joon-soo Park

IPC分类号： H01L21/302

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338

摘要： A method of forming a fine pattern of a semiconductor device using a fine pitch hard mask is provided. A first hard mask pattern including first line patterns formed on an etch target layer of a substrate with a first pitch is formed. A first layer including a top surface where a recess is formed between adjacent first line patterns is formed. A second hard mask pattern including second line patterns within the recess is formed. An anisotropic etching process is performed on the first layer using the first and the second line patterns as an etch mask. Another anisotropic etching process is performed on the etch target layer using the first and the second hard mask patterns as an etch mask.

摘要翻译： 提供了使用细间距硬掩模形成半导体器件的精细图案的方法。 形成包括形成在具有第一间距的基板的蚀刻目标层上的第一线图案的第一硬掩模图案。 形成包括在相邻的第一线图案之间形成有凹部的顶面的第一层。 形成包括凹部内的第二线图案的第二硬掩模图案。 使用第一和第二线图案作为蚀刻掩模在第一层上进行各向异性蚀刻处理。 使用第一和第二硬掩模图案作为蚀刻掩模在蚀刻目标层上执行另一种各向异性蚀刻工艺。

公开(公告)号：US20060234166A1

公开(公告)日：2006-10-19

申请号：US11367437

申请日：2006-03-06

申请人： Ji-young Lee ,  Sang-gyun Woo ,  Joon-soo Park

发明人： Ji-young Lee ,  Sang-gyun Woo ,  Joon-soo Park

IPC分类号： G03F7/26

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338

摘要： A method of forming a fine pattern of a semiconductor device using a fine pitch hard mask is provided. A first hard mask pattern including first line patterns formed on an etch target layer of a substrate with a first pitch is formed. A first layer including a top surface where a recess is formed between adjacent first line patterns is formed. A second hard mask pattern including second line patterns within the recess is formed. An anisotropic etching process is performed on the first layer using the first and the second line patterns as an etch mask. Another anisotropic etching process is performed on the etch target layer using the first and the second hard mask patterns as an etch mask.

公开(公告)号：US20070284623A1

公开(公告)日：2007-12-13

申请号：US11802647

申请日：2007-05-24

申请人： Sang-Jin Kim ,  Gi-sung Yeo ,  Joon-soo Park ,  Han-ku Cho ,  Sang-gyun Woo ,  Min-jong Hong

发明人： Sang-Jin Kim ,  Gi-sung Yeo ,  Joon-soo Park ,  Han-ku Cho ,  Sang-gyun Woo ,  Min-jong Hong

IPC分类号： H01L29/76 ,  H01L29/745

CPC分类号： H01L27/0207 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7827

摘要： A semiconductor device includes a substrate, and a plurality of active pillars arranged in a pattern of alternating even and odd rows and alternating even and odd columns, each active pillar extending from the substrate and including a channel portion, wherein the odd columns include active pillars spaced at a first pitch, the first pitch being determined in the column direction, the even columns include active pillars spaced at the first pitch, the even rows include active pillars spaced at a third pitch, the third pitch being determined in the row direction the odd rows include active pillars spaced at the third pitch, and active pillars in the even columns are offset by a second pitch from active pillars in the odd columns, the second pitch being determined in the column direction.

摘要翻译： 半导体器件包括衬底和布置成交替的偶数行和奇数行以及交替的偶数和奇数列的多个有源柱，每个有源柱从衬底延伸并且包括沟道部分，其中奇数列包括有源柱 以第一间距间隔开，第一间距是在列方向上确定的，偶数列包括以第一节距间隔开的活动柱，偶数行包括以第三节距间隔开的有效柱，第三间距在行方向上确定 奇数行包括在第三间距处间隔开的活动柱，并且偶数列中的活动柱由奇数列中的活动柱偏移第二间距，第二间距在列方向上确定。

公开(公告)号：US08242018B2

公开(公告)日：2012-08-14

申请号：US12943142

申请日：2010-11-10

申请人： Ji-young Lee ,  Hyun-jae Kang ,  Sang-gyun Woo

发明人： Ji-young Lee ,  Hyun-jae Kang ,  Sang-gyun Woo

IPC分类号： H01L21/44

CPC分类号： H01L21/76816 ,  H01L21/76897

摘要： A semiconductor device has a structure of contacts whose size and pitch are finer that those that can be produced under the resolution provided by conventional photolithography. The contact structure includes a semiconductor substrate, an interlayer insulating layer disposed on the substrate, annular spacers situated in the interlayer insulating layer, first contacts surrounded by the spacers, and a second contact buried in the interlayer insulating layer between each adjacent pair of the first spacers. The contact structure is formed by forming first contact holes in the interlayer insulating layer, forming the spacers over the sides of the first contact holes to leave second contact holes within the first contact holes, etching the interlayer insulating layer from between the spacers using the first spacers as an etch mask to form third contact holes, and filling the first and second contact holes with conductive material. In this way, the pitch of the contacts can be half that of the first contact holes.

摘要翻译： 半导体器件具有接触的结构，其尺寸和间距比通过常规光刻提供的分辨率可以产生的那些更小。 所述接触结构包括半导体衬底，设置在所述衬底上的层间绝缘层，位于所述层间绝缘层中的环形间隔物，被所述间隔物包围的第一接触部以及埋在所述层间绝缘层中的每个相邻的所述第一接触层 间隔物 接触结构通过在层间绝缘层中形成第一接触孔而形成，在第一接触孔的侧面上形成间隔物以在第一接触孔内留下第二接触孔，使用第一接触孔从间隔物之间​​蚀刻层间绝缘层 间隔物作为蚀刻掩模以形成第三接触孔，并且用导电材料填充第一和第二接触孔。 以这种方式，触点的间距可以是第一接触孔的间距的一半。

公开(公告)号：US07855408B2

公开(公告)日：2010-12-21

申请号：US11367436

申请日：2006-03-06

申请人： Ji-young Lee ,  Hyun-jae Kang ,  Sang-gyun Woo

发明人： Ji-young Lee ,  Hyun-jae Kang ,  Sang-gyun Woo

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L29/788 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L21/76816 ,  H01L21/76897

摘要： A semiconductor device has a structure of contacts whose size and pitch are finer that those that can be produced under the resolution provided by conventional photolithography. The contact structure includes a semiconductor substrate, an interlayer insulating layer disposed on the substrate, annular spacers situated in the interlayer insulating layer, first contacts surrounded by the spacers, and a second contact buried in the interlayer insulating layer between each adjacent pair of the first spacers. The contact structure is formed by forming first contact holes in the interlayer insulating layer, forming the spacers over the sides of the first contact holes to leave second contact holes within the first contact holes, etching the interlayer insulating layer from between the spacers using the first spacers as an etch mask to form third contact holes, and filling the first and second contact holes with conductive material. In this way, the pitch of the contacts can be half that of the first contact holes.

摘要翻译： 半导体器件具有接触的结构，其尺寸和间距比通过常规光刻提供的分辨率可以产生的那些更小。 所述接触结构包括半导体衬底，设置在所述衬底上的层间绝缘层，位于所述层间绝缘层中的环形间隔物，被所述间隔物包围的第一接触部以及埋在所述层间绝缘层中的每个相邻的所述第一接触层 间隔物 接触结构通过在层间绝缘层中形成第一接触孔而形成，在第一接触孔的侧面上形成间隔物以在第一接触孔内留下第二接触孔，使用第一接触孔从间隔物之间​​蚀刻层间绝缘层 间隔物作为蚀刻掩模以形成第三接触孔，并且用导电材料填充第一和第二接触孔。 以这种方式，触点的间距可以是第一接触孔的间距的一半。

公开(公告)号：US20110076846A1

公开(公告)日：2011-03-31

申请号：US12943142

申请日：2010-11-10

申请人： Ji-young Lee ,  Hyun-jae Kang ,  Sang-gyun Woo

发明人： Ji-young Lee ,  Hyun-jae Kang ,  Sang-gyun Woo

IPC分类号： H01L21/283

CPC分类号： H01L21/76816 ,  H01L21/76897

摘要： A semiconductor device has a structure of contacts whose size and pitch are finer that those that can be produced under the resolution provided by conventional photolithography. The contact structure includes a semiconductor substrate, an interlayer insulating layer disposed on the substrate, annular spacers situated in the interlayer insulating layer, first contacts surrounded by the spacers, and a second contact buried in the interlayer insulating layer between each adjacent pair of the first spacers. The contact structure is formed by forming first contact holes in the interlayer insulating layer, forming the spacers over the sides of the first contact holes to leave second contact holes within the first contact holes, etching the interlayer insulating layer from between the spacers using the first spacers as an etch mask to form third contact holes, and filling the first and second contact holes with conductive material. In this way, the pitch of the contacts can be half that of the first contact holes.

摘要翻译： 半导体器件具有接触的结构，其尺寸和间距比通过常规光刻提供的分辨率可以产生的那些更小。 所述接触结构包括半导体衬底，设置在所述衬底上的层间绝缘层，位于所述层间绝缘层中的环形间隔物，被所述间隔物包围的第一接触部以及埋在所述层间绝缘层中的每个相邻的所述第一接触层 间隔物 接触结构通过在层间绝缘层中形成第一接触孔而形成，在第一接触孔的侧面上形成间隔物以在第一接触孔内留下第二接触孔，使用第一接触孔从间隔物之间​​蚀刻层间绝缘层 间隔物作为蚀刻掩模以形成第三接触孔，并且用导电材料填充第一和第二接触孔。 以这种方式，触点的间距可以是第一接触孔的间距的一半。

公开(公告)号：US20070128823A1

公开(公告)日：2007-06-07

申请号：US11634142

申请日：2006-12-06

申请人： Ji-young Lee ,  Sang-gyun Woo

发明人： Ji-young Lee ,  Sang-gyun Woo

IPC分类号： H01L21/20

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/32139

摘要： A method of fabricating a semiconductor integrated circuit device is disclosed. The method may include forming an etching target layer on a semiconductor substrate, forming a sacrificial mold layer on the etching target layer, forming a photoresist pattern of a first image on the sacrificial mold layer, patterning the sacrificial mold layer using the photoresist pattern of the first image as an etching mask to form sacrificial molds, removing the photoresist pattern of the first image, forming a mask which fills portions between the sacrificial molds and may be an inverse image of the first image and etching the sacrificial molds and the etching target layer using the mask as the etching mask.

摘要翻译： 公开了制造半导体集成电路器件的方法。 该方法可以包括在半导体衬底上形成蚀刻目标层，在蚀刻目标层上形成牺牲模层，在牺牲模层上形成第一图像的光刻胶图案，使用 第一图像作为蚀刻掩模以形成牺牲模具，去除第一图像的光致抗蚀剂图案，形成填充牺牲模具之间的部分的掩模，并且可以是第一图像的反像，并蚀刻牺牲模具和蚀刻目标层 使用掩模作为蚀刻掩模。