公开(公告)号：US20070284623A1

公开(公告)日：2007-12-13

申请号：US11802647

申请日：2007-05-24

申请人： Sang-Jin Kim ,  Gi-sung Yeo ,  Joon-soo Park ,  Han-ku Cho ,  Sang-gyun Woo ,  Min-jong Hong

发明人： Sang-Jin Kim ,  Gi-sung Yeo ,  Joon-soo Park ,  Han-ku Cho ,  Sang-gyun Woo ,  Min-jong Hong

IPC分类号： H01L29/76 ,  H01L29/745

CPC分类号： H01L27/0207 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7827

摘要： A semiconductor device includes a substrate, and a plurality of active pillars arranged in a pattern of alternating even and odd rows and alternating even and odd columns, each active pillar extending from the substrate and including a channel portion, wherein the odd columns include active pillars spaced at a first pitch, the first pitch being determined in the column direction, the even columns include active pillars spaced at the first pitch, the even rows include active pillars spaced at a third pitch, the third pitch being determined in the row direction the odd rows include active pillars spaced at the third pitch, and active pillars in the even columns are offset by a second pitch from active pillars in the odd columns, the second pitch being determined in the column direction.

摘要翻译： 半导体器件包括衬底和布置成交替的偶数行和奇数行以及交替的偶数和奇数列的多个有源柱，每个有源柱从衬底延伸并且包括沟道部分，其中奇数列包括有源柱 以第一间距间隔开，第一间距是在列方向上确定的，偶数列包括以第一节距间隔开的活动柱，偶数行包括以第三节距间隔开的有效柱，第三间距在行方向上确定 奇数行包括在第三间距处间隔开的活动柱，并且偶数列中的活动柱由奇数列中的活动柱偏移第二间距，第二间距在列方向上确定。

公开(公告)号：US07221014B2

公开(公告)日：2007-05-22

申请号：US11015993

申请日：2004-12-17

申请人： Doo-hoon Goo ,  Jung-hyeon Lee ,  Gi-sung Yeo ,  Han-ku Cho ,  Sang-gyun Woo

发明人： Doo-hoon Goo ,  Jung-hyeon Lee ,  Gi-sung Yeo ,  Han-ku Cho ,  Sang-gyun Woo

IPC分类号： H01L29/74 ,  H01L29/76

CPC分类号： H01L27/10888 ,  H01L27/0207 ,  H01L27/10814

摘要： DRAM devices include a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction and intersecting the word lines. A plurality of active regions is provided that are electrically coupled to the word lines and the bit lines. Each of the active regions defines a single unit memory cell having an area of 6F2 in terms of a minimum line width F. Each of the active regions may be overlapped by only one word line and the active regions may be defined by an isolation region.

摘要翻译： DRAM装置包括沿第一方向延伸的多个字线和沿第二方向延伸并与字线相交的多个位线。 提供了多个有源区域，其被电耦合到字线和位线。 每个有源区域以最小线宽度F来限定具有6F 2的面积的单个单元存储单元。每个有源区域可以仅由一条字线重叠，并且有源区域 可以由隔离区限定。

公开(公告)号：US20050266646A1

公开(公告)日：2005-12-01

申请号：US11080891

申请日：2005-03-16

申请人： Doo-hoon Goo ,  Si-hyeung Lee ,  Han-ku Cho ,  Sang-gyun Woo ,  Gi-sung Yeo

发明人： Doo-hoon Goo ,  Si-hyeung Lee ,  Han-ku Cho ,  Sang-gyun Woo ,  Gi-sung Yeo

IPC分类号： H01L21/76 ,  H01L21/00 ,  H01L21/308 ,  H01L21/8242 ,  H01L27/02

CPC分类号： H01L27/10876 ,  H01L21/3083 ,  H01L27/0207

摘要： There are provided a method of forming a trench for a recessed channel of a transistor and a layout for the same. A layout for the recessed channel according to one aspect of the present invention is formed such that an open region is extended across at least one of a first active region in a lateral direction, and also across another second active region in parallel with the first active region in a diagonal direction, and the extension is cut not to reach an isolation region between two third active regions that are in parallel with the second active region in a diagonal direction, and have noses facing each other in a longitudinal direction, and the layout includes an alignment of a plurality of open regions, which are discontinuously aligned. An etch mask is formed using the layout, and a semiconductor substrate is etched using the etch mask, and a trench for a recessed channel is formed on the active region.

摘要翻译： 提供了一种形成用于晶体管的凹槽的沟槽的方法及其布局。 根据本发明的一个方面的凹陷通道的布局被形成为使得开放区域跨越横向方向上的第一有源区域中的至少一个延伸，并且还跨越与第一活性物体平行的另一个第二有源区域 区域，并且延伸部被切割成不能在对角线方向上到达与第二有源区域平行的两个第三有源区域之间的隔离区域，并且在纵向方向上具有彼此面对的鼻子，并且布局 包括不连续对准的多个开放区域的对准。 使用布局形成蚀刻掩模，并且使用蚀刻掩模蚀刻半导体衬底，并且在有源区上形成用于凹陷沟道的沟槽。

公开(公告)号：US07259065B2

公开(公告)日：2007-08-21

申请号：US11080891

申请日：2005-03-16

申请人： Doo-hoon Goo ,  Si-hyeung Lee ,  Han-ku Cho ,  Sang-gyun Woo ,  Gi-sung Yeo

发明人： Doo-hoon Goo ,  Si-hyeung Lee ,  Han-ku Cho ,  Sang-gyun Woo ,  Gi-sung Yeo

IPC分类号： H01L21/336

CPC分类号： H01L27/10876 ,  H01L21/3083 ,  H01L27/0207

摘要： There are provided a method of forming a trench for a recessed channel of a transistor and a layout for the same. A layout for the recessed channel according to one aspect of the present invention is formed such that an open region is extended across at least one of a first active region in a lateral direction, and also across another second active region in parallel with the first active region in a diagonal direction, and the extension is cut not to reach an isolation region between two third active regions that are in parallel with the second active region in a diagonal direction, and have noses facing each other in a longitudinal direction, and the layout includes an alignment of a plurality of open regions, which are discontinuously aligned. An etch mask is formed using the layout, and a semiconductor substrate is etched using the etch mask, and a trench for a recessed channel is formed on the active region.

摘要翻译： 提供了一种形成用于晶体管的凹槽的沟槽的方法及其布局。 根据本发明的一个方面的凹陷通道的布局被形成为使得开放区域跨越横向方向上的第一有源区域中的至少一个延伸，并且还跨越与第一活性物体平行的另一个第二有源区域 区域，并且延伸部被切割成不能在对角线方向上到达与第二有源区域平行的两个第三有源区域之间的隔离区域，并且在纵向方向上具有彼此面对的鼻子，并且布局 包括不连续对准的多个开放区域的对准。 使用布局形成蚀刻掩模，并且使用蚀刻掩模蚀刻半导体衬底，并且在有源区上形成用于凹陷沟道的沟槽。

公开(公告)号：US20050269615A1

公开(公告)日：2005-12-08

申请号：US11015993

申请日：2004-12-17

申请人： Doo-hoon Goo ,  Jung-hyeon Lee ,  Gi-sung Yeo ,  Han-ku Cho ,  Sang-gyun Woo

发明人： Doo-hoon Goo ,  Jung-hyeon Lee ,  Gi-sung Yeo ,  Han-ku Cho ,  Sang-gyun Woo

IPC分类号： H01L27/108 ,  H01L21/8242 ,  H01L27/02 ,  H01L29/74

CPC分类号： H01L27/10888 ,  H01L27/0207 ,  H01L27/10814

摘要： DRAM devices include a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction and intersecting the word lines. A plurality of active regions is provided that are electrically coupled to the word lines and the bit lines. Each of the active regions defines a single unit memory cell having an area of 6F2 in terms of a minimum line width F. Each of the active regions may be overlapped by only one word line and the active regions may be defined by an isolation region.

摘要翻译： DRAM装置包括沿第一方向延伸的多个字线和沿第二方向延伸并与字线相交的多个位线。 提供了多个有源区域，其被电耦合到字线和位线。 每个有源区域以最小线宽度F来限定具有6F 2的面积的单个单元存储单元。每个有源区域可以仅由一条字线重叠，并且有源区域 可以由隔离区限定。

公开(公告)号：US20110269294A1

公开(公告)日：2011-11-03

申请号：US13181655

申请日：2011-07-13

申请人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

发明人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

IPC分类号： H01L21/762

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76816

摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.

摘要翻译： 形成硬掩模的方法采用双重图案化技术。 第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。 第一牺牲图案的特征彼此间隔开第一间距。 然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。 去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。 然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。 可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

公开(公告)号：US20100197139A1

公开(公告)日：2010-08-05

申请号：US12759771

申请日：2010-04-14

申请人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

发明人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

IPC分类号： H01L21/311

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76816

摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.

摘要翻译： 形成硬掩模的方法采用双重图案化技术。 第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。 第一牺牲图案的特征彼此间隔开第一间距。 然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。 去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。 然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。 可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

公开(公告)号：US07732341B2

公开(公告)日：2010-06-08

申请号：US11727124

申请日：2007-03-23

申请人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

发明人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

IPC分类号： H01L21/302

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76816

摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.

摘要翻译： 形成硬掩模的方法采用双重图案化技术。 第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。 第一牺牲图案的特征彼此间隔开第一间距。 然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。 去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。 然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。 可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

公开(公告)号：US08278221B2

公开(公告)日：2012-10-02

申请号：US13181655

申请日：2011-07-13

申请人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

发明人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

IPC分类号： H01L21/331

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76816

摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.

摘要翻译： 形成硬掩模的方法采用双重图案化技术。 第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。 第一牺牲图案的特征彼此间隔开第一间距。 然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。 去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。 然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。 可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

公开(公告)号：US08003543B2

公开(公告)日：2011-08-23

申请号：US12759771

申请日：2010-04-14

申请人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

发明人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

IPC分类号： H01L21/302

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76816

摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.

摘要翻译： 形成硬掩模的方法采用双重图案化技术。 第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。 第一牺牲图案的特征彼此间隔开第一间距。 然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。 去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。 然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。 可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。