利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

116 条记录 (耗时 0.023 秒)

    Semiconductor device having fine contacts and method of fabricating the same
    1.
    发明授权
    Semiconductor device having fine contacts and method of fabricating the same 有权
    具有微细接触的半导体器件及其制造方法

    公开(公告)号：US08242018B2

    公开(公告)日：2012-08-14

    申请号：US12943142

    申请日：2010-11-10

    申请人： Ji-young Lee ,  Hyun-jae Kang ,  Sang-gyun Woo

    发明人： Ji-young Lee ,  Hyun-jae Kang ,  Sang-gyun Woo

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76816 ,  H01L21/76897

    摘要： A semiconductor device has a structure of contacts whose size and pitch are finer that those that can be produced under the resolution provided by conventional photolithography. The contact structure includes a semiconductor substrate, an interlayer insulating layer disposed on the substrate, annular spacers situated in the interlayer insulating layer, first contacts surrounded by the spacers, and a second contact buried in the interlayer insulating layer between each adjacent pair of the first spacers. The contact structure is formed by forming first contact holes in the interlayer insulating layer, forming the spacers over the sides of the first contact holes to leave second contact holes within the first contact holes, etching the interlayer insulating layer from between the spacers using the first spacers as an etch mask to form third contact holes, and filling the first and second contact holes with conductive material. In this way, the pitch of the contacts can be half that of the first contact holes.

    摘要翻译： 半导体器件具有接触的结构，其尺寸和间距比通过常规光刻提供的分辨率可以产生的那些更小。 所述接触结构包括半导体衬底，设置在所述衬底上的层间绝缘层，位于所述层间绝缘层中的环形间隔物，被所述间隔物包围的第一接触部以及埋在所述层间绝缘层中的每个相邻的所述第一接触层 间隔物 接触结构通过在层间绝缘层中形成第一接触孔而形成，在第一接触孔的侧面上形成间隔物以在第一接触孔内留下第二接触孔，使用第一接触孔从间隔物之间​​蚀刻层间绝缘层 间隔物作为蚀刻掩模以形成第三接触孔，并且用导电材料填充第一和第二接触孔。 以这种方式，触点的间距可以是第一接触孔的间距的一半。

    Method of forming pattern
    2.
    发明授权
    Method of forming pattern 有权
    形成图案的方法

    公开(公告)号：US07842451B2

    公开(公告)日：2010-11-30

    申请号：US12511538

    申请日：2009-07-29

    申请人： Cha-Won Koh ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Myoung-Ho Jung

    发明人： Cha-Won Koh ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Myoung-Ho Jung

    IPC分类号： G03F1/00 ,  G03F7/00

    CPC分类号： G03F7/11 ,  G03F7/0752 ,  G03F7/40 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/31138 ,  H01L21/31144

    摘要： Disclosed is a method of forming a pattern. A first organic polymer layer is formed on a substrate on which an underlying layer, and then a second organic polymer layer, which has an opening partially exposing the first organic polymer layer, is formed on the first organic polymer layer. Next, a silicon-containing polymer layer is formed on the second organic polymer layer to cover the opening. The silicon-containing polymer layer is oxidized and simultaneously the second organic polymer layer and the first organic polymer layer are ashed by oxygen plasma to form a pattern having an anisotropy-shape. The underlying layer is etched using the silicon-containing polymer layer and the first organic polymer layer as an etching mask to form a pattern.

    摘要翻译： 公开了形成图案的方法。 在第一有机聚合物层上形成第一有机聚合物层，在其上具有下层，然后形成具有部分暴露第一有机聚合物层的开口的第二有机聚合物层。 接下来，在第二有机聚合物层上形成含硅聚合物层以覆盖开口。 含硅聚合物层被氧化，同时第二有机聚合物层和第一有机聚合物层被氧等离子体灰化，形成具有各向异性形状的图案。 使用含硅聚合物层和第一有机聚合物层作为蚀刻掩模蚀刻下层，以形成图案。

    Multi-exposure semiconductor fabrication mask sets and methods of fabricating such multi-exposure mask sets
    6.
    发明授权
    Multi-exposure semiconductor fabrication mask sets and methods of fabricating such multi-exposure mask sets 有权
    多曝光半导体制造掩模组和制造这种多曝光掩模组的方法

    公开(公告)号：US07604907B2

    公开(公告)日：2009-10-20

    申请号：US11243401

    申请日：2005-10-04

    申请人： Doo-Youl Lee ,  Seok-Hwan Oh ,  Gi-Sung Yeo ,  Sang-Gyun Woo ,  Sook Lee ,  Joo-On Park ,  Sung-Gon Jung

    发明人： Doo-Youl Lee ,  Seok-Hwan Oh ,  Gi-Sung Yeo ,  Sang-Gyun Woo ,  Sook Lee ,  Joo-On Park ,  Sung-Gon Jung

    IPC分类号： G03F1/00

    CPC分类号： G03F7/70466 ,  G03F1/00

    摘要： Mask sets are provided which may be used to define a first pattern region that has a first pitch pattern and a second pattern region that has a second pitch pattern during the fabrication of a semiconductor device. These mask sets may include a first mask that has a first exposure region in which a first halftone pattern defines the first pattern region and a first screen region in which a first shield layer covers the second pattern region. These mask sets may further include a second mask that has a second exposure region in which a second halftone pattern defines the second pattern region and a second screen region in which a second shield layer covers the first pattern region. The second shield layer also extends from the second screen region to cover a portion of the second halftone pattern.

    摘要翻译： 提供掩模组，其可以用于限定在制造半导体器件期间具有第一间距图案的第一图案区域和具有第二间距图案的第二图案区域。 这些掩模组可以包括具有第一曝光区域的第一掩模，其中第一半色调图案限定第一图案区域和第一屏蔽区域，其中第一屏蔽层覆盖第二图案区域。 这些掩模组还可以包括具有第二曝光区域的第二掩模，其中第二半色调图案限定第二图案区域和第二屏蔽区域，其中第二屏蔽层覆盖第一图案区域。 第二屏蔽层也从第二屏幕区域延伸以覆盖第二半色调图案的一部分。

    Photomask for measuring lens aberration, method of its manufacture, and method of its use
    7.
    发明授权
    Photomask for measuring lens aberration, method of its manufacture, and method of its use 失效
    用于测量透镜像差的光掩模，其制造方法及其使用方法

    公开(公告)号：US07403276B2

    公开(公告)日：2008-07-22

    申请号：US11388887

    申请日：2006-03-23

    申请人： Jang-Ho Shin ,  Han-Ku Cho ,  Sang-Gyun Woo ,  Suk-Joo Lee

    发明人： Jang-Ho Shin ,  Han-Ku Cho ,  Sang-Gyun Woo ,  Suk-Joo Lee

    IPC分类号： G01B9/00

    CPC分类号： G01M11/0264 ,  G03F1/44 ,  G03F7/706

    摘要： A photomask for measuring lens aberration, a method of manufacturing the photomask, and a method of measuring lens aberration using the photomask are provided. In an embodiment, the photomask includes a transparent substrate having first and second surfaces. A reference pattern group and an encoded pattern group are formed on the second surface of the transparent substrate, spaced apart from each other. An aperture that includes a Fresnel zone is formed to face the second surface on the second surface of the transparent substrate. Light throughput and measurement efficiency are improved.

    摘要翻译： 提供了用于测量透镜像差的光掩模，制造光掩模的方法以及使用光掩模测量透镜像差的方法。 在一个实施例中，光掩模包括具有第一和第二表面的透明基板。 参考图案组和编码图案组形成在透明基板的彼此间隔开的第二表面上。 包括菲涅耳区的孔径形成为与透明基板的第二表面上的第二表面相对。 光通量和测量效率得到提高。

    Mask patterns for semiconductor device fabrication and related methods
    8.
    发明授权
    Mask patterns for semiconductor device fabrication and related methods 失效
    半导体器件制造的掩模图案及相关方法

    公开(公告)号：US07361609B2

    公开(公告)日：2008-04-22

    申请号：US11232703

    申请日：2005-09-22

    申请人： Jung-hwan Hah ,  Hyun-woo Kim ,  Mitsuhiro Hata ,  Sang-gyun Woo

    发明人： Jung-hwan Hah ,  Hyun-woo Kim ,  Mitsuhiro Hata ,  Sang-gyun Woo

    IPC分类号： H01L21/302

    CPC分类号： H01L21/0274 ,  G03F7/405 ,  H01L21/0273 ,  H01L21/31144

    摘要： Methods of forming an integrated circuit device may include forming a resist pattern on a layer of an integrated circuit device with portions of the layer being exposed through openings of the resist pattern. An organic-inorganic hybrid siloxane network film may be formed on the resist pattern. Portions of the layer exposed through the resist pattern and the organic-inorganic hybrid siloxane network film may then be removed. Related structures are also discussed.

    摘要翻译： 形成集成电路器件的方法可以包括在集成电路器件的层上形成抗蚀剂图案，其中该层的部分通过抗蚀剂图案的开口露出。 可以在抗蚀剂图案上形成有机 - 无机杂化硅氧烷网膜。 然后可以去除通过抗蚀剂图案暴露的层的部分和有机 - 无机杂化硅氧烷网膜。 还讨论了相关结构。