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    Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell
    1.
    发明授权
    Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell 有权
    适用于将多值数据存储在单个存储单元中的非易失性半导体存储器件

    公开(公告)号：US07864591B2

    公开(公告)日：2011-01-04

    申请号：US12652418

    申请日：2010-01-05

    申请人： Tomoharu Tanaka ,  Jian Chen

    发明人： Tomoharu Tanaka ,  Jian Chen

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459 ,  G11C16/3481 ,  G11C2211/5621 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.

    摘要翻译： 非易失性半导体存储器件包括电数据可重写非易失性半导体存储单元和用于在存储单元中写入数据的写入电路，写入电路通过提供写入电压Vpgm和写入控制将数据写入存储单元 电压VBL到存储器单元，响应于存储单元的第一写入状态的到来改变写入控制电压VBL的值，继续写入存储单元中的数据，并且禁止写入数据的任何操作 该存储单元响应于存储单元的第二写入状态的进入而进一步将写入控制电压VBL的值改变为Vdd。

    Behavior based programming of non-volatile memory
    2.
    发明授权
    Behavior based programming of non-volatile memory 有权
    非易失性存储器的基于行为的编程

    公开(公告)号：US07633807B2

    公开(公告)日：2009-12-15

    申请号：US11624052

    申请日：2007-01-17

    申请人： Jian Chen ,  Jeffrey W. Lutze ,  Yan Li ,  Daniel C. Guterman ,  Tomoharu Tanaka

    发明人： Jian Chen ,  Jeffrey W. Lutze ,  Yan Li ,  Daniel C. Guterman ,  Tomoharu Tanaka

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459

    摘要： The process for programming a set of memory cells is improved by adapting the programming process based on behavior of the memory cells. For example, a set of program pulses is applied to the word line for a set of flash memory cells. A determination is made as to which memory cells are easier to program and which memory cells are harder to program. Bit line voltages (or other parameters) can be adjusted based on the determination of which memory cells are easier to program and which memory cells are harder to program. The programming process will then continue with the adjusted bit line voltages (or other parameters).

    摘要翻译： 通过基于存储器单元的行为调整编程过程来改进用于对一组存储器单元进行编程的过程。 例如，一组编程脉冲被施加到一组闪存单元的字线。 确定哪些存储器单元更容易编程，哪些存储器单元难以编程。 可以基于确定哪些存储器单元更容易编程以及哪些存储器单元难以编程来调整位线电压（或其他参数）。 然后，编程过程将继续调整的位线电压（或其他参数）。

    Methods for identifying non-volatile memory elements with poor subthreshold slope or weak transconductance
    3.
    发明授权
    Methods for identifying non-volatile memory elements with poor subthreshold slope or weak transconductance 有权
    用于识别具有差的亚阈值斜率或弱跨导的非易失性存储元件的方法

    公开(公告)号：US07046555B2

    公开(公告)日：2006-05-16

    申请号：US10665685

    申请日：2003-09-17

    申请人： Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Kazunori Kanebako ,  Tomoharu Tanaka

    发明人： Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Kazunori Kanebako ,  Tomoharu Tanaka

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3495 ,  G11C16/04 ,  G11C16/349 ,  G11C29/50 ,  G11C29/50004

    摘要： A number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behavior of degraded storage elements by cycling cells and then programming them to a state above the ground state and the reading them with a control gate voltage below the threshold voltage of this state to see if they still conduct. A second set of embodiments focuses on weak transconductance behavior by reading programmed cells with a control gate voltage well above the threshold voltage. A third set of embodiments alters the voltage levels at the source-drain regions of the storage elements. The current-voltage curve of a good storage element is relatively stable under this shift in bias conditions, while degraded elements exhibit a larger shift. The amount of shift can be used to differentiate the good elements from the bad.

    摘要翻译： 用于鉴定具有差的亚阈值斜率和降低的跨导的细胞的许多方法。 第一组技术集中在通过循环单元对劣化的存储元件的差的亚阈值行为进行编程，然后将它们编程到高于基态的状态，并以低于该状态的阈值电压的控制栅极电压读取它们，以查看它们是否仍然 进行。 第二组实施例通过利用远高于阈值电压的控制栅极电压读取编程单元来侧重于弱跨导行为。 第三组实施例改变存储元件的源极 - 漏极区域处的电压电平。 在偏置条件下的这种偏移下，良好存储元件的电流 - 电压曲线相对稳定，而退化元件表现出较大的偏移。 偏移量可以用来区分好的元素和坏的元素。

    Non-volatile semiconductor memory with large erase blocks storing cycle counts
    4.
    发明申请
    Non-volatile semiconductor memory with large erase blocks storing cycle counts 有权

    公开(公告)号：US20050099870A1

    公开(公告)日：2005-05-12

    申请号：US11003046

    申请日：2004-12-02

    申请人： Jian Chen ,  Tomoharu Tanaka

    发明人： Jian Chen ,  Tomoharu Tanaka

    IPC分类号： G06F12/00 ,  G11C11/24 ,  G11C11/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  H01L27/115

    CPC分类号： G11C11/5635 ,  G06F11/1068 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/3427 ,  G11C16/3459 ,  G11C16/349 ,  G11C2211/5641 ,  G11C2211/5646

    摘要： In a flash EEPROM system that is divided into separately erasable blocks of memory cells with multiple pages of user data being stored in each block, a count of the number of erase cycles that each block has endured is stored in one location within the block, such as in spare cells of only one page or distributed among header regions of multiple pages. The page or pages containing the block cycle count are initially read from each block that is being erased, the cycle count temporarily stored, the block erased and an updated cycle count is then written back into the block location. User data is then programmed into individual pages of the block as necessary. The user data is preferably stored in more than two states per memory cell storage element, in which case the cycle count can be stored in binary in a manner to speed up the erase process and reduce disturbing effects on the erased state that writing the updated cycle count can cause. An error correction code calculated from the cycle count may be stored with it, thereby allowing validation of the stored cycle count.

    Multi-state nonvolatile memory capable of reducing effects of coupling between storage elements
    8.
    发明授权
    Multi-state nonvolatile memory capable of reducing effects of coupling between storage elements 有权
    能够减少存储元件之间的耦合效应的多状态非易失性存储器

    公开(公告)号：US06807095B2

    公开(公告)日：2004-10-19

    申请号：US10323534

    申请日：2002-12-18

    申请人： Jian Chen ,  Tomoharu Tanaka ,  Yupin Fong ,  Khandker N. Quader

    发明人： Jian Chen ,  Tomoharu Tanaka ,  Yupin Fong ,  Khandker N. Quader

    IPC分类号： G11C1634

    CPC分类号： G11C11/5628 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/3404 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459

    摘要： A non-volatile memory system having an array of memory cells with at least one storage element each is operated with a plurality of storage level ranges per storage element. A flash electrically erasable and programmable read only memory (EEPROM) is an example, wherein the storage elements are electrically floating gates. The memory is operated to minimize the effect of charge coupled between adjacent floating gates, by programming some cells a second time after adjacent cells have been programmed. The second programming step also compacts a distribution of charge levels within at least some of the programming states. This increases the separation between states and/or allows more states to be included within a given storage window. An implementation that is described is for a NAND type of flash EEPROM.

    摘要翻译： 具有每个具有至少一个存储元件的存储器单元阵列的非易失性存储器系统每个存储元件具有多个存储级别范围。 闪存电可擦除和可编程只读存储器（EEPROM）是示例，其中存储元件是电浮动栅极。 操作存储器以通过在相邻单元被编程之后第二次编程一些单元来最小化耦合在相邻浮动栅极之间的电荷的影响。 第二编程步骤还压缩至少一些编程状态下的电荷水平分布。 这增加了状态之间的分离和/或允许在给定的存储窗口内包含更多的状态。 所描述的实现方案是用于NAND型闪存EEPROM。

    Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell
    9.
    发明授权
    Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell 有权
    适用于将多值数据存储在单个存储单元中的非易失性半导体存储器件

    公开(公告)号：US08208311B2

    公开(公告)日：2012-06-26

    申请号：US12967227

    申请日：2010-12-14

    申请人： Tomoharu Tanaka ,  Jian Chen

    发明人： Tomoharu Tanaka ,  Jian Chen

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459 ,  G11C16/3481 ,  G11C2211/5621 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.

    摘要翻译： 非易失性半导体存储器件包括电数据可重写非易失性半导体存储单元和用于在存储单元中写入数据的写入电路，写入电路通过提供写入电压Vpgm和写入控制将数据写入存储单元 电压VBL到存储器单元，响应于存储单元的第一写入状态的到来改变写入控制电压VBL的值，继续写入存储单元中的数据，并且禁止写入数据的任何操作 该存储单元响应于存储单元的第二写入状态的进入而进一步将写入控制电压VBL的值改变为Vdd。

    Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell
    10.
    发明授权
    Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell 有权
    适用于将多值数据存储在单个存储单元中的非易失性半导体存储器件

    公开(公告)号：US07672168B2

    公开(公告)日：2010-03-02

    申请号：US12168283

    申请日：2008-07-07

    申请人： Tomoharu Tanaka ,  Jian Chen

    发明人： Tomoharu Tanaka ,  Jian Chen

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459 ,  G11C16/3481 ,  G11C2211/5621 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.

    摘要翻译： 非易失性半导体存储器件包括电数据可重写非易失性半导体存储单元和用于在存储单元中写入数据的写入电路，写入电路通过提供写入电压Vpgm和写入控制将数据写入存储单元 电压VBL到存储器单元，响应于存储单元的第一写入状态的到来改变写入控制电压VBL的值，继续写入存储单元中的数据，并且禁止写入数据的任何操作 该存储单元响应于存储单元的第二写入状态的进入而进一步将写入控制电压VBL的值改变为Vdd。