公开(公告)号：US07883945B2

公开(公告)日：2011-02-08

申请号：US11835904

申请日：2007-08-08

申请人： Jin-Goo Jung ,  Hyun-Uk Oh

发明人： Jin-Goo Jung ,  Hyun-Uk Oh

IPC分类号： H01L21/84

CPC分类号： H01L27/1214 ,  H01L27/1255 ,  H01L27/1288

摘要： A method or manufacturing an array substrate at a low cost. Silicon patterns are formed. A first impurity is implanted at a high concentration. Gate metal patterns are formed. A second impurity is implanted. The first impurity is implanted at a low concentration. A pixel electrode is formed. The first impurity is simultaneously implanted into partial portions of the pixel pattern part, the storage pattern part, and the driving pattern part.

摘要翻译： 以低成本制造阵列基板的方法。 形成硅图形。 以高浓度植入第一杂质。 形成栅极金属图案。 植入第二种杂质。 第一种杂质以低浓度植入。 形成像素电极。 第一杂质同时注入到像素图案部分，存储图案部分和驱动图案部分的部分部分中。

公开(公告)号：US20080035937A1

公开(公告)日：2008-02-14

申请号：US11835904

申请日：2007-08-08

申请人： Jin-Goo Jung ,  Hyun-Uk Oh

发明人： Jin-Goo Jung ,  Hyun-Uk Oh

IPC分类号： H01L33/00 ,  H01L21/00

CPC分类号： H01L27/1214 ,  H01L27/1255 ,  H01L27/1288

摘要： A method or manufacturing an array substrate at a low cost. Silicon patterns are formed. A first impurity is implanted at a high concentration. Gate metal patterns are formed. A second impurity is implanted. The first impurity is implanted at a low concentration. A pixel electrode is formed. The first impurity is simultaneously implanted into partial portions of the pixel pattern part, the storage pattern part, and the driving pattern part.

摘要翻译： 以低成本制造阵列基板的方法。 形成硅图形。 以高浓度植入第一杂质。 形成栅极金属图案。 植入第二种杂质。 第一种杂质以低浓度植入。 形成像素电极。 第一杂质同时注入到像素图案部分，存储图案部分和驱动图案部分的部分部分中。

公开(公告)号：US08164097B2

公开(公告)日：2012-04-24

申请号：US12326841

申请日：2008-12-02

申请人： Kyung-Min Park ,  Jin-Goo Jung ,  Chun-Gi You

发明人： Kyung-Min Park ,  Jin-Goo Jung ,  Chun-Gi You

IPC分类号： H01L27/14

CPC分类号： H01L27/1288 ,  G02F1/136227 ,  H01L27/1214 ,  H01L27/3244 ,  H01L51/56

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a thin film transistor including a gate electrode, a drain electrode, a source electrode and a semiconductor on a substrate; forming a first passivation layer on the drain and the source electrodes; forming a transparent conductive layer on the first passivation layer; etching the transparent conductive layer using a photoresist as an etch mask to expose the portion of the first passivation layer and to form a pixel electrode connected the drain electrode; ashing the first passivation layer and the photoresist; and removing the photoresist.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，其包括：在衬底上形成包括栅电极，漏电极，源电极和半导体的薄膜晶体管; 在漏极和源电极上形成第一钝化层; 在所述第一钝化层上形成透明导电层; 使用光致抗蚀剂蚀刻透明导电层作为蚀刻掩模以暴露第一钝化层的部分并形成连接漏电极的像素电极; 灰化第一钝化层和光致抗蚀剂; 并去除光致抗蚀剂。

公开(公告)号：US07646017B2

公开(公告)日：2010-01-12

申请号：US11218211

申请日：2005-08-31

申请人： Jin-Goo Jung ,  Kyung-Min Park ,  Chun-Gi You

发明人： Jin-Goo Jung ,  Kyung-Min Park ,  Chun-Gi You

IPC分类号： H01L31/00

CPC分类号： H01L27/12 ,  G02F1/13454 ,  G02F2001/13629 ,  G02F2201/50 ,  H01L27/124

摘要： Improved thin film transistor array panels are provided. In one embodiment, a panel includes a plurality of gate lines, data lines, and a plurality of switching elements connected to the gate lines and the data lines. An interlayer insulating layer is formed between the gate lines and the data lines. A passivation layer covering the gate lines, the data lines, and the switching elements is also provided having a plurality of first contact holes exposing portions of the data lines, wherein the switching elements and the pixel electrodes are connected through the first contact holes. A plurality of contact assistants are formed on the passivation layer and are connected to the data lines through a plurality of second contact holes in the passivation layer. A plurality of auxiliary lines are connected to the data lines through a plurality of third contact holes in the interlayer insulating layer.

摘要翻译： 提供了改进的薄膜晶体管阵列面板。 在一个实施例中，面板包括连接到栅极线和数据线的多条栅极线，数据线和多个开关元件。 在栅极线和数据线之间形成层间绝缘层。 还提供了覆盖栅极线，数据线和开关元件的钝化层，其具有暴露数据线部分的多个第一接触孔，其中开关元件和像素电极通过第一接触孔连接。 多个接触助剂形成在钝化层上，并通过钝化层中的多个第二接触孔与数据线连接。 多个辅助线通过层间绝缘层中的多个第三接触孔连接到数据线。

公开(公告)号：US07636145B2

公开(公告)日：2009-12-22

申请号：US11353823

申请日：2006-02-14

申请人： Jin-Goo Jung ,  Chun-Gi You ,  Chul-Ho Kim ,  Kyung-Min Park ,  Il-Gon Kim

发明人： Jin-Goo Jung ,  Chun-Gi You ,  Chul-Ho Kim ,  Kyung-Min Park ,  Il-Gon Kim

IPC分类号： G02F1/1345

CPC分类号： G02F1/136227 ,  G02F1/13458 ,  G02F2001/13456 ,  H05K1/117 ,  H05K3/323 ,  H05K3/361 ,  H05K2201/09436 ,  H05K2201/09472

摘要： In a display apparatus and a manufacturing method of the display apparatus, the display apparatus includes a display panel having signal lines and an insulating layer, and a signal generator electrically connected to the signal lines and adhering to the display panel. The signal lines include pads formed at ends thereof, respectively. The organic insulating layer is partially removed such that the via holes are formed between the pads of the signal lines to reduce a step-difference between an area in which the pads are formed and an area in which the pads are not formed. Thus, the display apparatus may enhance the coupling force between the signal generator and the display panel.

摘要翻译： 在显示装置的显示装置和制造方法中，显示装置包括具有信号线和绝缘层的显示面板，以及电连接到信号线并附着在显示面板上的信号发生器。 信号线分别包括在其端部形成的焊盘。 有机绝缘层被部分去除，使得通孔形成在信号线的焊盘之间，以减小其中形成焊盘的区域与不形成焊盘的区域之间的阶差。 因此，显示装置可以增强信号发生器和显示面板之间的耦合力。

公开(公告)号：US20060258061A1

公开(公告)日：2006-11-16

申请号：US11256358

申请日：2005-10-21

申请人： Jin-Goo Jung ,  Chun-Gi You

发明人： Jin-Goo Jung ,  Chun-Gi You

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L27/12 ,  H01L27/124

摘要： A thin film transistor array panel is provided, which includes: a semiconductor layer; a first insulating layer on the semiconductor layer; a gate line including a first amorphous silicon layer and a metal; a second insulating layer covering the gate line; and a data line formed on the second insulating layer. A variously tapered structure of the signal line may be formed by providing an amorphous silicon layer having good adhesion characteristics. The adhesion between the metal layer and the amorphous silicon layer may be improved by performing a thermal treatment process such that the contact resistance may be reduced therebetween. Accordingly, the characteristics and reliability of the TFT may be improved.

摘要翻译： 提供薄膜晶体管阵列面板，其包括：半导体层; 半导体层上的第一绝缘层; 包括第一非晶硅层和金属的栅极线; 覆盖所述栅极线的第二绝缘层; 以及形成在第二绝缘层上的数据线。 可以通过提供具有良好粘合特性的非晶硅层来形成信号线的各种锥形结构。 可以通过进行热处理工艺来改善金属层和非晶硅层之间的粘合性，使得其间的接触电阻可能降低。 因此，可以提高TFT的特性和可靠性。

公开(公告)号：US07528021B2

公开(公告)日：2009-05-05

申请号：US11229245

申请日：2005-09-15

申请人： Kyung-Min Park ,  Jin-Goo Jung ,  Chun-Gi You ,  Jae-Byoung Chae ,  Tae-Ill Kim

发明人： Kyung-Min Park ,  Jin-Goo Jung ,  Chun-Gi You ,  Jae-Byoung Chae ,  Tae-Ill Kim

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/4908 ,  H01L29/66757

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a semiconductor layer of polysilicon on an insulating substrate; forming a gate insulating layer on the semiconductor layer; forming a gate electrode on the gate insulating layer; forming a source region and a drain region by doping conductive impurities in the semiconductor layer; forming an interlayer insulating layer covering the gate electrode; forming a source electrode and a drain electrode respectively connected to the source and the drain regions; forming a passivation layer covering the source and the drain electrodes; forming a pixel electrode connected to the drain electrode; and forming a first alignment key when forming one selected from the semiconductor layer, the gate electrode, the source and the drain electrodes, and the pixel electrode, wherein one selected from the semiconductor layer, the gate electrode, the source and the drain electrodes, and the pixel electrode is at least formed by photolithography process using a photoresist pattern as an etch mask, and a second alignment key completely covering the first alignment key is formed at the same layer as the photoresist pattern.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，其包括：在绝缘衬底上形成多晶硅半导体层; 在所述半导体层上形成栅极绝缘层; 在栅极绝缘层上形成栅电极; 通过掺杂半导体层中的导电杂质形成源区和漏区; 形成覆盖所述栅电极的层间绝缘层; 形成分别连接到源区和漏区的源电极和漏电极; 形成覆盖源极和漏极的钝化层; 形成连接到所述漏电极的像素电极; 以及在形成从半导体层，栅电极，源极和漏极以及像素电极中选择的一个时形成第一对准键，其中从半导体层，栅电极，源电极和漏电极中选择一个， 并且至少通过使用光致抗蚀剂图案作为蚀刻掩模的光刻工艺形成像素电极，并且在与光致抗蚀剂图案相同的层处形成完全覆盖第一对准键的第二对准键。

公开(公告)号：US20060065894A1

公开(公告)日：2006-03-30

申请号：US11232736

申请日：2005-09-22

申请人： Jin-Goo Jung ,  Chun-Gi You ,  Kyung-Min Park

发明人： Jin-Goo Jung ,  Chun-Gi You ,  Kyung-Min Park

IPC分类号： H01L29/786 ,  H01L21/84

CPC分类号： H01L27/1222 ,  H01L27/1214 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/78621

摘要： A thin film transistor array panel is provided, which includes a substrate having a display area and driver, a polysilicon layer formed on the substrate and including channel, source, and drain regions, and lightly doped regions disposed between the channel region and the source and drain regions, and having an impurity concentration lower than the source and the drain regions, a gate insulating layer formed on the polysilicon layer, an impurity layer formed on the gate insulating layer and overlapping the channel region of the polysilicon layer and doped with impurities, a gate electrode formed on the impurity layer, an interlayer insulating layer covering the gate electrode and having first and second contact holes respectively exposing the source and drain regions, and source and drain electrodes respectively connected to the source and drain regions via the first and the second contact holes.

摘要翻译： 提供一种薄膜晶体管阵列面板，其包括具有显示区域和驱动器的衬底，形成在衬底上并包括沟道，源极和漏极区域的多晶硅层以及设置在沟道区域和源极之间的轻掺杂区域，以及 漏区，杂质浓度低于源极和漏极区，形成在多晶硅层上的栅极绝缘层，形成在栅极绝缘层上并与多晶硅层的沟道区重叠并掺杂有杂质的杂质层， 形成在所述杂质层上的栅极电极，覆盖所述栅电极并具有分别暴露所述源极和漏极区域的第一和第二接触孔以及分别连接到所述源极和漏极区域的源极和漏极的层间绝缘层， 第二接触孔。

公开(公告)号：US20060060858A1

公开(公告)日：2006-03-23

申请号：US11229245

申请日：2005-09-15

申请人： Kyung-Min Park ,  Jin-Goo Jung ,  Chun-Gi You ,  Jae-Byoung Chae ,  Tae-Ill Kim

发明人： Kyung-Min Park ,  Jin-Goo Jung ,  Chun-Gi You ,  Jae-Byoung Chae ,  Tae-Ill Kim

IPC分类号： H01L29/76

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/4908 ,  H01L29/66757

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a semiconductor layer of polysilicon on an insulating substrate; forming a gate insulating layer on the semiconductor layer; forming a gate electrode on the gate insulating layer; forming a source region and a drain region by doping conductive impurities in the semiconductor layer; forming an interlayer insulating layer covering the gate electrode; forming a source electrode and a drain electrode respectively connected to the source and the drain regions; forming a passivation layer covering the source and the drain electrodes; forming a pixel electrode connected to the drain electrode; and forming a first alignment key when forming one selected from the semiconductor layer, the gate electrode, the source and the drain electrodes, and the pixel electrode, wherein one selected from the semiconductor layer, the gate electrode, the source and the drain electrodes, and the pixel electrode is at least formed by photolithography process using a photoresist pattern as an etch mask, and a second alignment key completely covering the first alignment key is formed at the same layer as the photoresist pattern.

公开(公告)号：US20060049407A1

公开(公告)日：2006-03-09

申请号：US11218211

申请日：2005-08-31

申请人： Jin-Goo Jung ,  Kyung-Min Park ,  Chun-Gi You

发明人： Jin-Goo Jung ,  Kyung-Min Park ,  Chun-Gi You

IPC分类号： H01L31/036

CPC分类号： H01L27/12 ,  G02F1/13454 ,  G02F2001/13629 ,  G02F2201/50 ,  H01L27/124

摘要： Improved thin film transistor array panels are provided. In one embodiment, a panel includes a plurality of gate lines, data lines, and a plurality of switching elements connected to the gate lines and the data lines. An interlayer insulating layer is formed between the gate lines and the data lines. A passivation layer covering the gate lines, the data lines, and the switching elements is also provided having a plurality of first contact holes exposing portions of the data lines, wherein the switching elements and the pixel electrodes are connected through the first contact holes. A plurality of contact assistants are formed on the passivation layer and are connected to the data lines through a plurality of second contact holes in the passivation layer. A plurality of auxiliary lines are connected to the data lines through a plurality of third contact holes in the interlayer insulating layer.

摘要翻译： 提供了改进的薄膜晶体管阵列面板。 在一个实施例中，面板包括连接到栅极线和数据线的多条栅极线，数据线和多个开关元件。 在栅极线和数据线之间形成层间绝缘层。 还提供了覆盖栅极线，数据线和开关元件的钝化层，其具有暴露数据线部分的多个第一接触孔，其中开关元件和像素电极通过第一接触孔连接。 多个接触助剂形成在钝化层上，并通过钝化层中的多个第二接触孔与数据线连接。 多个辅助线通过层间绝缘层中的多个第三接触孔连接到数据线。