公开(公告)号：US12127347B2

公开(公告)日：2024-10-22

申请号：US18041042

申请日：2022-08-30

Applicant: HONOR DEVICE CO., LTD.

Inventor： Zhijie Xu

IPC: H05K1/18 ,  H05K3/32

CPC classification number: H05K1/183 ,  H05K3/328 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2201/10037

Abstract: Embodiments of this application are applied to the field of terminal technologies, and provide a PCB assembly and an electronic device, where the PCB assembly includes a PCB, a first conductor, a first battery, and a second battery. The PCB includes a groove area. The first battery and the second battery are disposed on different sides of the groove area. The first conductor is disposed in the groove area, and the first conductor is configured to connect the first battery and the second battery. That is, in the embodiments of this application, the first battery and the second battery are connected by using the first conductor in the groove area, which prevents a power cable connecting the first battery and the second battery from occupying an area on the PCB, thereby increasing an area in which other components can be installed on the PCB.

公开(公告)号：US12112881B2

公开(公告)日：2024-10-08

申请号：US18523280

申请日：2023-11-29

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Rikiya Sano ,  Masayuki Yoneda

IPC: H01F27/29 ,  H01F27/28 ,  H05K1/18

CPC classification number: H01F27/292 ,  H05K1/18 ,  H01F27/2804 ,  H05K2201/09381 ,  H05K2201/09472 ,  H05K2201/1003

Abstract: An inductor component includes a component body having a mounting surface and a top surface and provided therein with a spiral inductor wiring line advancing in the extending direction of a winding center axis. The inductor wiring line is connected to a first external electrode at a first end, and connected to a second external electrode at a second end. The component body includes: a first inclined surface connected to a first end of the mounting surface on a first side in a length direction and inclined toward the top surface as separating from the first end; and a second inclined surface connected to a second end of the mounting surface on a second side in the length direction and inclined toward the top surface as separating from the second end. The winding center axis extends in a direction parallel to the mounting surface and perpendicular to the length direction.

公开(公告)号：US20240170430A1

公开(公告)日：2024-05-23

申请号：US18515364

申请日：2023-11-21

Applicant: X Display Company Technology Limited

Inventor： Carl Prevatte ,  Christopher Bower ,  Ronald S. Cok ,  Matthew Meitl

IPC: H01L23/00 ,  H01L21/48 ,  H05K1/11 ,  H05K3/30 ,  H05K3/34

CPC classification number: H01L24/11 ,  H01L24/08 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H05K1/112 ,  H05K3/3436 ,  H01L21/4803 ,  H01L21/4846 ,  H01L2224/1144 ,  H01L2224/11466 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/1357 ,  H01L2224/1403 ,  H01L2224/1412 ,  H01L2224/1418 ,  H01L2224/16227 ,  H01L2224/1624 ,  H01L2224/17107 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/12044 ,  H01L2924/1304 ,  H05K3/305 ,  H05K2201/09409 ,  H05K2201/09472 ,  H05K2201/0979 ,  H05K2201/10143

Abstract: A component includes a plurality of electrical connections on a process side opposed to a back side of the component. Each electrical connection includes an electrically conductive multi-layer connection post protruding from the process side. A printed structure includes a destination substrate and one or more components. The destination substrate has two or more electrical contacts and each connection post is in contact with, extends into, or extends through an electrical contact of the destination substrate to electrically connect the electrical contacts to the connection posts. The connection posts or electrical contacts are deformed. Two or more connection posts can be electrically connected to a common electrical contact.

公开(公告)号：US11917757B2

公开(公告)日：2024-02-27

申请号：US17495851

申请日：2021-10-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiroki Maegawa

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/00 ,  H05K3/28

CPC classification number: H05K1/112 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0058 ,  H05K3/28 ,  H05K2201/09472 ,  H05K2203/1377

Abstract: A circuit board includes a substrate including first and second sections with different thicknesses, a protective layer, and mounting electrodes. The substrate includes a step surface connecting a first principal surface of the first section and a first principal surface of the second section. The mounting electrodes are on the first principal surface corresponding to an element to be mounted. The protective layer is disposed over the first principal surface, the step surface, and the first principal surface. The separation distance between the mounting electrode and the step surface is greater than or equal to the terminal-to-terminal distance between the mounting electrode and the mounting electrode.

公开(公告)号：US20230395766A1

公开(公告)日：2023-12-07

申请号：US18032212

申请日：2021-10-14

Applicant: TDK CORPORATION

Inventor： Tomohisa MITOSE ,  Kenichi KAWABATA ,  Susumu TANIGUCHI ,  Akiko SEKI

IPC: H01L33/62 ,  H01L23/00 ,  H05K1/18

CPC classification number: H01L33/62 ,  H01L24/16 ,  H01L24/13 ,  H05K1/181 ,  H01L24/73 ,  H01L24/32 ,  H01L2933/0066 ,  H01L2224/73204 ,  H01L2224/32237 ,  H01L24/81 ,  H01L2224/16237 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/81815 ,  H01L2224/81192 ,  H05K2201/10106 ,  H05K2201/09472 ,  H01L2924/12041 ,  H05K2201/09827

Abstract: A mounting board includes an electronic component having at least a pair of first terminals, and a circuit board having at least a pair of second terminals. The first terminal and the second terminal are bonded to each other by a bonding material. The first terminal, the second terminal, and the bonding material are disposed inside a recessed portion formed in a resin layer such that the periphery thereof is surrounded by the resin layer. When a total thickness of the first terminal, the second terminal, and the bonding material is a dimension h1, the dimension h1 is 1 μm to 20 μm. When a width of the first terminal is a dimension d1 and a width of the recessed portion of the resin layer is a dimension d2, a value of (dimension d2—dimension d1) is 10 μm or smaller.

公开(公告)号：US11658142B2

公开(公告)日：2023-05-23

申请号：US16947786

申请日：2020-08-17

Applicant: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft

Inventor： Heinz Moitzi ,  Johannes Stahr ,  Andreas Zluc

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H05K1/11 ,  H05K1/18 ,  H05K3/34

CPC classification number: H01L24/16 ,  H01L21/4846 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H05K1/111 ,  H05K1/181 ,  H05K3/3436 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/05572 ,  H01L2224/13019 ,  H01L2224/1607 ,  H01L2224/16059 ,  H01L2224/81143 ,  H01L2224/81345 ,  H01L2224/81801 ,  H05K2201/09472 ,  H05K2201/10636 ,  H05K2201/10727 ,  H05K2203/048

Abstract: A connection arrangement for forming a component carrier structure is disclosed. The connection arrangement includes a first electrically conductive connection element and a second electrically conductive connection element. The first connection element and the second connection element are configured such that, upon connecting the first connection element with the second connection element along a connection direction, a form fit is established between the first connection element and the second connection element that limits a relative motion between the first connection element and the second connection element in a plane perpendicular to the connection direction. A component carrier and a method of forming a component carrier structure are also disclosed.

公开(公告)号：US10014246B2

公开(公告)日：2018-07-03

申请号：US15284514

申请日：2016-10-03

Applicant: VIA Technologies, Inc.

Inventor： Chen-Yueh Kung

IPC: H05K1/11 ,  H05K1/18 ,  H01L23/498 ,  H05K3/00 ,  H05K3/40 ,  H01L23/13 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H05K3/28

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3185 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/10 ,  H01L2224/16157 ,  H01L2224/73204 ,  H05K1/112 ,  H05K1/119 ,  H05K1/181 ,  H05K3/0026 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/09472 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/0723 ,  H05K2203/107 ,  H05K2203/1476 ,  Y10T29/49156

Abstract: A circuit substrate has the following elements. A stacked circuit structure has a first surface and a second surface opposite thereto surface. A first patterned inner conductive layer is disposed on the first surface and has multiple pads. A first patterned outer conductive layer is disposed on the patterned inner conductive layer and has multiple conductive pillars, wherein each of the first conductive pillar is located on the corresponding first pad. The first dielectric layer covers the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer, and has multiple first concaves, wherein the first concave exposes the top and side of the corresponding first conductive pillar. A semiconductor package structure applied the above circuit substrate and a process for fabricating the same are also provided here.

公开(公告)号：US20180040544A1

公开(公告)日：2018-02-08

申请号：US15660718

申请日：2017-07-26

Applicant: Invensas Corporation

Inventor： Rajesh Emeka Katkar ,  Min Tao ,  Javier A. Delacruz ,  Hoki Kim ,  Akash Agrawal

IPC: H01L23/498 ,  H05K3/34 ,  H05K1/18 ,  H05K1/11 ,  H01L25/10 ,  H01L21/48

CPC classification number: H01L23/49805 ,  H01L21/4803 ,  H01L21/4846 ,  H01L21/4853 ,  H01L23/13 ,  H01L23/49833 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/48105 ,  H01L2224/48225 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2924/15159 ,  H01L2924/15162 ,  H01L2924/15172 ,  H01L2924/15331 ,  H01L2924/15333 ,  H05K1/117 ,  H05K1/141 ,  H05K1/144 ,  H05K1/181 ,  H05K3/3405 ,  H05K3/366 ,  H05K2201/049 ,  H05K2201/09472 ,  H05K2201/09745 ,  H05K2201/09845 ,  H05K2201/10159 ,  H05K2201/10522

Abstract: Multi-surface edge pads for vertical mount packages and methods of making package stacks are provided. Example substrates for vertical surface mount to a motherboard have multi-surface edge pads. The vertical mount substrates may be those of a laminate-based FlipNAND. The multi-surface edge pads have cutouts or recesses that expose more surfaces and more surface area of the substrate for bonding with the motherboard. The cutouts in the edge pads allow more solder to be used between the attachment surface of the substrate and the motherboard. The placement and geometry of the resulting solder joint is stronger and has less internal stress than conventional solder joints for vertical mounting. In an example process, blind holes can be drilled into a thickness of a substrate, and the blind holes plated with metal. The substrate can be cut in half though the plated holes to provide two substrates with plated multi-surface edge pads including the cutouts for mounting to the motherboard.

公开(公告)号：US09812387B2

公开(公告)日：2017-11-07

申请号：US15364143

申请日：2016-11-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li-Chuan Tsai ,  Chih-Cheng Lee

IPC: H05K1/11 ,  H05K1/03 ,  H05K1/16 ,  H05K7/00 ,  H05K1/18 ,  H01L23/498 ,  H05K1/02 ,  H05K3/36 ,  H05K3/00 ,  H05K3/22 ,  H05K3/40 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0266 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0158 ,  H05K2201/09472 ,  H05K2201/09527 ,  H05K2201/10204 ,  H05K2203/166 ,  Y02P70/611

Abstract: A semiconductor substrate includes: 1) a first dielectric structure having a first surface and a second surface opposite the first surface; 2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; 3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and 4) a second patterned conductive layer, disposed on the second surface of the first dielectric structure and including at least one conductive trace. The first dielectric structure defines at least one opening to expose a portion of the second patterned conductive layer.

公开(公告)号：US09795033B2

公开(公告)日：2017-10-17

申请号：US14096514

申请日：2013-12-04

Applicant: Panasonic Corporation

Inventor： Shingo Yoshioka ,  Hiroaki Fujiwara

IPC: H01L23/48 ,  H05K1/11 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  G11B5/48 ,  H05K1/18 ,  H05K3/18 ,  H01L21/66 ,  H01L23/31 ,  H01L21/56

CPC classification number: H05K1/11 ,  G11B5/486 ,  H01L21/565 ,  H01L22/12 ,  H01L23/3121 ,  H01L24/03 ,  H01L24/05 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/82 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73267 ,  H01L2224/82009 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/82931 ,  H01L2224/82947 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/111 ,  H05K1/117 ,  H05K1/181 ,  H05K3/184 ,  H05K2201/0376 ,  H05K2201/09472 ,  Y02P70/611 ,  Y10T428/1171 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A three-dimensional structure in which a wiring is provided on a surface is provided. At least a part of the surface of the three-dimensional structure includes an insulating layer containing filler. A recessed gutter for wiring is provided on the surface of the three-dimensional structure, and at least a part of a wiring conductor is embedded in the recessed gutter for wiring.