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公开(公告)号：US20060133145A1
公开(公告)日：2006-06-22
申请号：US11283646
申请日：2005-11-21
申请人： Jin-Sung Park , Dae-Seok Byeon
发明人： Jin-Sung Park , Dae-Seok Byeon
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C2216/14
摘要： A flash memory device is programmed by loading first data into a page buffer of a first mat. Second data is loaded into a page buffer of a second mat while programming the first data in a first memory block of the first mat.
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公开(公告)号：US20060082411A1
公开(公告)日：2006-04-20
申请号：US11167983
申请日：2005-06-27
申请人： Jin-Sung Park , Dae-Seok Byeon
发明人： Jin-Sung Park , Dae-Seok Byeon
IPC分类号： G05F1/10
CPC分类号： G05F1/575
摘要： Disclosed is a voltage regulator capable of reducing a set-up time. A driver is connected between a power supply terminal and the output terminal, and supplies a power supply voltage to the output terminal in response to a signal of a control node. A first signal generator provides a first signal to the control node when a voltage of the output terminal is lower than the target voltage. A second signal generator provides a second signal to the control node for a predetermined period of time when the voltage of the output terminal becomes higher than a detection voltage while the first signal generator is providing the first signal to the control node.
摘要翻译： 公开了一种能够减少设置时间的电压调节器。 驱动器连接在电源端子和输出端子之间，并且响应于控制节点的信号将电源电压提供给输出端子。 当输出端子的电压低于目标电压时，第一信号发生器向控制节点提供第一信号。 当第一信号发生器向控制节点提供第一信号时，第二信号发生器在输出端的电压变得高于检测电压的预定时间段内向控制节点提供第二信号。
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3.发明授权Flash memory devices and methods of programming the same by overlapping programming operations for multiple mats 有权闪存设备和通过重叠多个垫的编程操作对其编程的方法公开(公告)号：US07580284B2
公开(公告)日：2009-08-25
申请号：US12034968
申请日：2008-02-21
申请人： Jin-Sung Park , Dae-Seok Byeon
发明人： Jin-Sung Park , Dae-Seok Byeon
CPC分类号： G11C16/10 , G11C2216/14
摘要： A flash memory device is programmed by loading first data into a page buffer of a first mat. Second data is loaded into a page buffer of a second mat while programming the first data in a first memory block of the first mat.
摘要翻译： 通过将第一数据加载到第一垫的页缓冲器中来编程闪存器件。 第二数据被加载到第二垫的页缓冲器中，同时在第一垫的第一存储块中编程第一数据。
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公开(公告)号：US07315198B2
公开(公告)日：2008-01-01
申请号：US11167983
申请日：2005-06-27
申请人： Jin-Sung Park , Dae-Seok Byeon
发明人： Jin-Sung Park , Dae-Seok Byeon
CPC分类号： G05F1/575
摘要： Disclosed is a voltage regulator capable of reducing a set-up time. A driver is connected between a power supply terminal and the output terminal, and supplies a power supply voltage to the output terminal in response to a signal of a control node. A first signal generator provides a first signal to the control node when a voltage of the output terminal is lower than the target voltage. A second signal generator provides a second signal to the control node for a predetermined period of time when the voltage of the output terminal becomes higher than a detection voltage while the first signal generator is providing the first signal to the control node.
摘要翻译： 公开了一种能够减少设置时间的电压调节器。 驱动器连接在电源端子和输出端子之间，并且响应于控制节点的信号将电源电压提供给输出端子。 当输出端子的电压低于目标电压时，第一信号发生器向控制节点提供第一信号。 当第一信号发生器向控制节点提供第一信号时，第二信号发生器在输出端的电压变得高于检测电压的预定时间段内向控制节点提供第二信号。
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5.发明申请FLASH MEMORY DEVICES AND METHODS OF PROGRAMMING THE SAME BY OVERLAPPING PROGRAMMING OPERATIONS FOR MULTIPLE MATS 有权闪存存储器件及其编程方法通过重写多个程序的编程操作公开(公告)号：US20090296472A1
公开(公告)日：2009-12-03
申请号：US12541429
申请日：2009-08-14
申请人： Jin-Sung Park , Dae-Seok Byeon
发明人： Jin-Sung Park , Dae-Seok Byeon
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C2216/14
摘要： A flash memory device is programmed by loading first data into a page buffer of a first mat. Second data is loaded into a page buffer of a second mat while programming the first data in a first memory block of the first mat.
摘要翻译： 通过将第一数据加载到第一垫的页缓冲器中来编程闪存器件。 第二数据被加载到第二垫的页缓冲器中，同时在第一垫的第一存储块中编程第一数据。
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6.发明授权Flash memory devices and methods of programming the same by overlapping programming operations for multiple mats 有权闪存设备和通过重叠多个垫的编程操作对其编程的方法公开(公告)号：US07800971B2
公开(公告)日：2010-09-21
申请号：US12541429
申请日：2009-08-14
申请人： Jin-Sung Park , Dae-Seok Byeon
发明人： Jin-Sung Park , Dae-Seok Byeon
CPC分类号： G11C16/10 , G11C2216/14
摘要： A flash memory device is programmed by loading first data into a page buffer of a first mat. Second data is loaded into a page buffer of a second mat while programming the first data in a first memory block of the first mat.
摘要翻译： 通过将第一数据加载到第一垫的页缓冲器中来编程闪存器件。 第二数据被加载到第二垫的页缓冲器中，同时在第一垫的第一存储块中编程第一数据。
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7.发明授权Flash memory devices and methods of programming the same by overlapping programming operations for multiple mats 有权闪存设备和通过重叠多个垫的编程操作对其编程的方法公开(公告)号：US07349256B2
公开(公告)日：2008-03-25
申请号：US11283646
申请日：2005-11-21
申请人： Jin-Sung Park , Dae-Seok Byeon
发明人： Jin-Sung Park , Dae-Seok Byeon
CPC分类号： G11C16/10 , G11C2216/14
摘要： A flash memory device is programmed by loading first data into a page buffer of a first mat. Second data is loaded into a page buffer of a second mat while programming the first data in a first memory block of the first mat.
摘要翻译： 通过将第一数据加载到第一垫的页缓冲器中来编程闪存器件。 第二数据被加载到第二垫的页缓冲器中，同时在第一垫的第一存储块中编程第一数据。
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8.发明申请FLASH MEMORY DEVICES AND METHODS OF PROGRAMMING THE SAME BY OVERLAPPING PROGRAMMING OPERATIONS FOR MULTIPLE MATS 有权闪存存储器件及其编程方法通过重写多个程序的编程操作公开(公告)号：US20080137420A1
公开(公告)日：2008-06-12
申请号：US12034968
申请日：2008-02-21
申请人： Jin-Sung Park , Dae-Seok Byeon
发明人： Jin-Sung Park , Dae-Seok Byeon
IPC分类号： G11C16/06
CPC分类号： G11C16/10 , G11C2216/14
摘要： A flash memory device is programmed by loading first data into a page buffer of a first mat. Second data is loaded into a page buffer of a second mat while programming the first data in a first memory block of the first mat.
摘要翻译： 通过将第一数据加载到第一垫的页缓冲器中来编程闪存器件。 第二数据被加载到第二垫的页缓冲器中，同时在第一垫的第一存储块中编程第一数据。
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9.发明申请Flash memory devices having a voltage trimming circuit and methods of operating the same 审中-公开具有电压调整电路的闪存器件及其操作方法公开(公告)号：US20060056238A1
公开(公告)日：2006-03-16
申请号：US11023896
申请日：2004-12-28
申请人： Jin-Sung Park , Dae-Seok Byeon
发明人： Jin-Sung Park , Dae-Seok Byeon
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G11C16/28 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/5004 , G11C2211/5634 , G11C2216/26
摘要： A flash memory device includes a trimming circuit that is configured to generate a plurality of identification voltages associated with a plurality of memory cell threshold voltage states, respectively, and to trim the plurality of identification voltages responsive to trimming information.
摘要翻译： 闪速存储器件包括修整电路，其被配置为分别产生与多个存储单元阈值电压状态相关联的多个识别电压，并根据修整信息来修整多个识别电压。
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公开(公告)号：US09899394B2
公开(公告)日：2018-02-20
申请号：US15001877
申请日：2016-01-20
申请人： Sung-Min Hwang , Jee-Yong Kim , Dae-Seok Byeon
发明人： Sung-Min Hwang , Jee-Yong Kim , Dae-Seok Byeon
IPC分类号： H01L27/115 , H01L27/11578 , H01L27/11575 , H01L27/11573 , H01L27/11565 , H01L27/1157 , H01L27/11563 , H01L27/11582
CPC分类号： H01L27/115 , H01L27/11563 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L27/11582
摘要： A vertical memory device includes a plurality of gate electrodes at a plurality of levels, respectively, spaced apart from each other in a vertical direction substantially perpendicular to a top surface of a substrate, a channel extending in the vertical direction on the substrate and penetrating through the gate electrodes, and a plurality of contact plugs extending in the vertical direction and contacting the gate electrodes, respectively. At least one second contact plug is formed on a first gate electrode among the plurality of gate electrodes, and extends in the vertical direction.
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