公开(公告)号：US20050202606A1

公开(公告)日：2005-09-15

申请号：US11055928

申请日：2005-02-10

申请人： Jin-Taek Park ,  Hong-Soo Kim

发明人： Jin-Taek Park ,  Hong-Soo Kim

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8247 ,  H01L27/06 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/00

CPC分类号： H01L28/20 ,  H01L27/0629

摘要： A semiconductor device including a resistor and a method of forming the same. In the semiconductor device, a conductive pattern, which connects source regions, and a resistor are formed of the same material, which can be polysilicon. In the method, the conductive pattern and the resistor are simultaneously formed. Thus, it is possible to obtain a constant sheet resistance without an additional photo mask.

摘要翻译： 一种包括电阻器的半导体器件及其形成方法。 在半导体器件中，连接源极区域的导电图案和电阻器由可以是多晶硅的相同材料形成。 在该方法中，同时形成导电图案和电阻器。 因此，可以在没有附加的光掩模的情况下获得恒定的薄层电阻。

公开(公告)号：US06873016B2

公开(公告)日：2005-03-29

申请号：US10678586

申请日：2003-10-03

申请人： Jin-Taek Park ,  Hong-Soo Kim

发明人： Jin-Taek Park ,  Hong-Soo Kim

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8247 ,  H01L27/06 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L28/20 ,  H01L27/0629

摘要： A semiconductor device including a resistor and a method of forming the same. In the semiconductor device, a conductive pattern, which connects source regions, and a resistor are formed of the same material, which can be polysilicon. In the method, the conductive pattern and the resistor are simultaneously formed. Thus, it is possible to obtain a constant sheet resistance without an additional photo mask.

公开(公告)号：US08045383B2

公开(公告)日：2011-10-25

申请号：US11729169

申请日：2007-03-28

申请人： Jong-Sun Sel ,  Jung-Dal Choi ,  Young-Woo Park ,  Jin-Taek Park

发明人： Jong-Sun Sel ,  Jung-Dal Choi ,  Young-Woo Park ,  Jin-Taek Park

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/3427

摘要： A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a first plurality of word lines crossing the active region between a first ground select line and a first string select line, and about a same first spacing may be provided between adjacent ones of the first plurality of word lines. The second memory cell string may include a second plurality of word lines crossing the active region between a second ground select line and a second string select line, and about the same first spacing may be provided between adjacent ones of the second plurality of word lines. Moreover, the first ground select line may be between the second ground select line and the first plurality of word lines, and the second ground select line may be between the first ground select line and the second plurality of word lines. Moreover, portions of the active region between the first and second ground select lines may be free of word lines, and a second spacing between the first and second ground select lines may be at least about 3 times greater than the first spacing. Related methods are also discussed.

摘要翻译： 非易失性存储器件可以包括半导体衬底，其包括其表面处的有源区，有源区上的第一存储单元串和有源区上的第二存储单元串。 第一存储单元串可以包括与第一地选择线和第一串选择线之间的有源区域交叉的第一多个字线，并且可以在第一多个字线中相邻的字线之间提供约相同的第一间隔。 第二存储单元串可以包括与第二接地选择线和第二串选择线之间的有源区域交叉的第二多个字线，并且可以在相邻的第二多个字线之间提供约相同的第一间隔。 此外，第一接地选择线可以在第二接地选择线和第一多个字线之间，并且第二接地选择线可以在第一接地选择线和第二多个字线之间。 此外，第一和第二接地选择线之间的有源区域的部分可以没有字线，并且第一和第二接地选择线之间的第二间隔可以比第一间隔大至少约3倍。 还讨论了相关方法。

公开(公告)号：US07871921B2

公开(公告)日：2011-01-18

申请号：US11022240

申请日：2004-12-22

申请人： Jin-Taek Park ,  Jong-Ho Park ,  Sung-Hoi Hur ,  Hyun-Suk Kim

发明人： Jin-Taek Park ,  Jong-Ho Park ,  Sung-Hoi Hur ,  Hyun-Suk Kim

IPC分类号： H01L21/4763

CPC分类号： H01L21/76895 ,  H01L21/76877 ,  H01L23/485

摘要： An interconnection structure for a semiconductor device includes an inter-level insulation layer disposed on a semiconductor substrate. First contact constructions penetrate the inter-level insulation layer. Second contact constructions penetrate the inter-level insulation layer. Metal interconnections connect the first contact constructions to the second contact constructions on the inter-level insulation layer. The first contact constructions include first and second plugs stacked in sequence and the second contact constructions include the second plug.

摘要翻译： 半导体器件的互连结构包括设置在半导体衬底上的级间绝缘层。 第一接触结构穿透层间绝缘层。 第二接触构造穿透层间绝缘层。 金属互连将第一接触结构连接到层间绝缘层上的第二接触结构。 第一接触构造包括依次堆叠的第一和第二插塞，并且第二接触构造包括第二插塞。

公开(公告)号：US07799645B2

公开(公告)日：2010-09-21

申请号：US12232148

申请日：2008-09-11

申请人： Jung-Dal Choi ,  Young-Woo Park ,  Jin-Taek Park ,  Chung-Il Hyun

发明人： Jung-Dal Choi ,  Young-Woo Park ,  Jin-Taek Park ,  Chung-Il Hyun

IPC分类号： H01L21/8236

CPC分类号： H01L21/8236 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573

摘要： An embodiment of a semiconductor device includes a substrate including a cell region and a peripheral region; a cell gate pattern on the cell region; and a peripheral gate pattern on the peripheral region, wherein a first cell insulation layer, a second cell insulation layer, and a third cell insulation layer may be between the substrate and the cell gate pattern, a first peripheral insulation layer, a second peripheral insulation layer, and a third peripheral insulation layer may be between the substrate and the peripheral gate pattern, and the second cell insulation layer and the third cell insulation layer include the same material as the respective second peripheral insulation layer and third peripheral insulation layer.

摘要翻译： 半导体器件的实施例包括：包括单元区域和周边区域的衬底; 单元格区域上的单元格栅图案; 以及周边区域上的外围栅极图案，其中第一电池绝缘层，第二电池绝缘层和第三电池绝缘层可以在衬底和电池栅极图案之间，第一外围绝缘层，第二外围绝缘层 层和第三外围绝缘层可以在基板和外围栅极图案之间，并且第二电池绝缘层和第三电池绝缘层包括与相应的第二外围绝缘层和第三外围绝缘层相同的材料。

公开(公告)号：US20090085096A1

公开(公告)日：2009-04-02

申请号：US12238476

申请日：2008-09-26

申请人： Jin-Taek Park ,  Won-Seok Jung

发明人： Jin-Taek Park ,  Won-Seok Jung

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11573 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/11565

摘要： Provided are nonvolatile memory devices and methods of forming nonvolatile memory devices. Nonvolatile memory devices include a device isolation layer that defines an active region in a substrate. Nonvolatile memory devices further include a first insulating layer, a nonconductive charge storage pattern, a second insulating layer and a control gate line that are sequentially disposed on the active region. The charge storage pattern includes a horizontal portion and a protrusion disposed on an upper portion of an edge of the horizontal portion.

摘要翻译： 提供了非易失性存储器件和形成非易失性存储器件的方法。 非易失性存储器件包括限定衬底中的有源区的器件隔离层。 非易失性存储器件还包括顺序地设置在有源区上的第一绝缘层，非导电电荷存储图案，第二绝缘层和控制栅极线。 电荷存储图案包括水平部分和设置在水平部分的边缘的上部上的突起。

公开(公告)号：US09343452B2

公开(公告)日：2016-05-17

申请号：US14542709

申请日：2014-11-17

申请人： Tae-Hwan Yun ,  Jin-Taek Park

发明人： Tae-Hwan Yun ,  Jin-Taek Park

IPC分类号： H01L27/02 ,  H01L23/495 ,  H01L23/522 ,  H01L23/528 ,  H01L27/105

CPC分类号： H01L27/0207 ,  H01L23/49517 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/105 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a substrate having a cell region and a connection region. A plurality of gate electrodes is stacked in a vertical direction in the cell region of the substrate. Conductive pads that are electrically connected to a peripheral circuit extend horizontally from the gate electrodes to the connection region. The conductive pads form a cascade structure in the connection region. Contact plugs that have different vertical lengths are electrically connected to respective ones of the conductive pads. The conductive pads have contact portions that are thicker in the vertical direction than the gate electrodes.

摘要翻译： 半导体器件包括具有单元区域和连接区域的衬底。 多个栅电极在基板的单元区域中沿垂直方向堆叠。 电连接到外围电路的导电焊盘从栅电极向连接区水平延伸。 导电焊盘在连接区域中形成级联结构。 具有不同垂直长度的接触塞电连接到相应的导电焊盘。 导电焊盘具有在垂直方向上比栅电极更厚的接触部分。

公开(公告)号：US08675409B2

公开(公告)日：2014-03-18

申请号：US13463060

申请日：2012-05-03

申请人： Jong-Sun Sel ,  Jung-Dal Choi ,  Young-Woo Park ,  Jin-Taek Park

发明人： Jong-Sun Sel ,  Jung-Dal Choi ,  Young-Woo Park ,  Jin-Taek Park

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/3427

摘要： A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a ground select line crossing the active region, and a string select line crossing the active region and spaced apart from the ground select line. A plurality of memory cell word lines may cross the active region between the ground select line and the string select line with about a same first spacing provided between adjacent ones of the plurality of word lines and between a last of the plurality of memory cell word lines and the string select line. A second spacing may be provided between the ground select line and a first of the plurality of memory cell word lines.

摘要翻译： 非易失性存储器件可以包括半导体衬底，其包括其表面处的有源区，与有源区交叉的接地选择线，以及与有源区交叉并与地选线相隔的串选择线。 多个存储单元字线可以与地线选择线和弦选择线之间的有源区域相交，并且与多个字线中的相邻字线之间以及多个存储单元字线中的最后一个之间提供大致相同的第一间隔 和字符串选择行。 可以在接地选择线和多个存储单元字线中的第一个之间提供第二间隔。

公开(公告)号：US20110101439A1

公开(公告)日：2011-05-05

申请号：US12987440

申请日：2011-01-10

申请人： Jin-Taek Park ,  Jong-Ho Park ,  Sung-Hoi Hur ,  Hyun-Suk Kim

发明人： Jin-Taek Park ,  Jong-Ho Park ,  Sung-Hoi Hur ,  Hyun-Suk Kim

IPC分类号： H01L29/78

CPC分类号： H01L21/76895 ,  H01L21/76877 ,  H01L23/485

摘要： An interconnection structure for a semiconductor device includes an inter-level insulation layer disposed on a semiconductor substrate. First contact constructions penetrate the inter-level insulation layer. Second contact constructions penetrate the inter-level insulation layer. Metal interconnections connect the first contact constructions to the second contact constructions on the inter-level insulation layer. The first contact constructions include first and second plugs stacked in sequence and the second contact constructions include the second plug.

摘要翻译： 半导体器件的互连结构包括设置在半导体衬底上的级间绝缘层。 第一接触结构穿透层间绝缘层。 第二接触构造穿透层间绝缘层。 金属互连将第一接触结构连接到层间绝缘层上的第二接触结构。 第一接触构造包括依次堆叠的第一和第二插塞，并且第二接触构造包括第二插塞。

公开(公告)号：US07867883B2

公开(公告)日：2011-01-11

申请号：US12146653

申请日：2008-06-26

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park ,  Byeong-In Choe

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park ,  Byeong-In Choe

IPC分类号： H01L21/425 ,  H01L29/06

CPC分类号： H01L27/1157 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/42352 ,  H01L29/7851 ,  H01L29/792

摘要： A method of fabricating a semiconductor device includes forming a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate, forming a gate structure on the surface of the active region, and performing an ion implantation process to form source/drain regions in the active region at opposite sides of the gate structure. The source/drain regions respectively include a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region. The first impurity region has a doping concentration that is greater than that of the second impurity regions. Related devices are also discussed.

摘要翻译： 一种制造半导体器件的方法包括：形成鳍状有源区，包括相对的侧壁和从衬底突出的表面，在有源区的表面上形成栅极结构，并执行离子注入工艺以形成源极/漏极 在栅极结构的相对侧的有源区中的区域。 源极/漏极区域分别包括有源区的表面中的第一杂质区域和有源区的相对侧壁中的第二杂质区。 第一杂质区域的掺杂浓度大于第二杂质区域的掺杂浓度。 还讨论了相关设备。