公开(公告)号：US20050085025A1

公开(公告)日：2005-04-21

申请号：US10605678

申请日：2003-10-17

申请人： Jin-Tau Huang ,  Chung-Peng Hao ,  Yi-Nan Chen ,  Tse-Yao Huang

发明人： Jin-Tau Huang ,  Chung-Peng Hao ,  Yi-Nan Chen ,  Tse-Yao Huang

IPC分类号： H01L21/28 ,  H01L21/336

CPC分类号： H01L21/28247 ,  H01L21/28061

摘要： A method of forming a gate structure. First, a substrate is provided, and a gate oxide layer, a polysilicon layer, a suicide layer, and a cap layer are consecutively formed onto the substrate. Then, an etching process is performed to etch a portion of the cap layer, the silicide layer, and the polysilicon layer and stop on the polysilicon layer for forming a stacked gate. Thereafter, a portion of the silicide layer exposed on sidewalls of the stacked gate is removed to form a recess. A passivation layer is deposited to fill the recess. The remaining polysilicon layer and the gate oxide layer outside the sidewalls of the stacked gate structure are removed.

摘要翻译： 一种形成栅极结构的方法。 首先，提供基板，并且在基板上连续地形成栅氧化层，多晶硅层，硅化物层和盖层。 然后，进行蚀刻处理以蚀刻覆盖层，硅化物层和多晶硅层的一部分，并停留在多晶硅层上以形成堆叠栅极。 此后，去除暴露在堆叠栅极的侧壁上的硅化物层的一部分以形成凹陷。 沉积钝化层以填充凹部。 除去堆叠栅结构的侧壁外的剩余多晶硅层和栅氧化层。

公开(公告)号：US07094638B2

公开(公告)日：2006-08-22

申请号：US10605678

申请日：2003-10-17

申请人： Jin-Tau Huang ,  Chung-Peng Hao ,  Yi-Nan Chen ,  Tse-Yao Huang

发明人： Jin-Tau Huang ,  Chung-Peng Hao ,  Yi-Nan Chen ,  Tse-Yao Huang

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/28247 ,  H01L21/28061

摘要： A method of forming a gate structure. First, a substrate is provided, and a gate oxide layer, a polysilicon layer, a silicide layer, and a cap layer are consecutively formed onto the substrate. Then, an etching process is performed to etch a portion of the cap layer, the silicide layer, and the polysilicon layer and stop on the polysilicon layer for forming a stacked gate. Thereafter, a portion of the silicide layer exposed on sidewalls of the stacked gate is removed to form a recess. A passivation layer is deposited to fill the recess. The remaining polysilicon layer and the gate oxide layer outside the sidewalls of the stacked gate structure are removed.

摘要翻译： 一种形成栅极结构的方法。 首先，提供基板，并且在基板上连续地形成栅氧化层，多晶硅层，硅化物层和盖层。 然后，进行蚀刻处理以蚀刻覆盖层，硅化物层和多晶硅层的一部分，并停留在多晶硅层上以形成堆叠栅极。 此后，去除暴露在堆叠栅极的侧壁上的硅化物层的一部分以形成凹陷。 沉积钝化层以填充凹部。 除去堆叠栅结构的侧壁外的剩余多晶硅层和栅氧化层。

公开(公告)号：US06884714B2

公开(公告)日：2005-04-26

申请号：US10612859

申请日：2003-07-03

申请人： Tse-Yao Huang ,  Yi-Nan Chen ,  Chung-Peng Hao

发明人： Tse-Yao Huang ,  Yi-Nan Chen ,  Chung-Peng Hao

IPC分类号： H01L21/762 ,  H01L21/4763

CPC分类号： H01L21/76232

摘要： A method of forming shallow trench isolation with chamfered corners. First, a pad insulating layer, a first mask layer, and a second mask layer are sequentially formed on a substrate. The second mask layer, the first mask layer, and the pad insulating layer are patterned to form an opening exposing a portion of the substrate. Next, the substrate is etched using the patterned second mask layer as a mask to form a trench therein. Next, part of the second mask layer is removed to expose the first mask layer adjacent to the trench and result in the second mask layer having a tapered profile. Finally, the second mask layer, the first mask layer, the pad insulating layer, and the substrate are etched along the tapered profile of the second mask layer to chamfer corners of the trench.

摘要翻译： 形成具有倒角的浅沟槽隔离的方法。 首先，在衬底上依次形成衬垫绝缘层，第一掩模层和第二掩模层。 对第二掩模层，第一掩模层和焊盘绝缘层进行图案化以形成露出衬底的一部分的开口。 接下来，使用图案化的第二掩模层作为掩模蚀刻衬底，以在其中形成沟槽。 接下来，去除第二掩模层的一部分以暴露与沟槽相邻的第一掩模层，并导致第二掩模层具有锥形轮廓。 最后，沿着第二掩模层的锥形轮廓蚀刻第二掩模层，第一掩模层，焊盘绝缘层和衬底以倒角沟槽的角部。

公开(公告)号：US20050054193A1

公开(公告)日：2005-03-10

申请号：US10709264

申请日：2004-04-26

申请人： Tien-Sung Chen ,  Yi-Nan Chen ,  Jin-Tau Huang

发明人： Tien-Sung Chen ,  Yi-Nan Chen ,  Jin-Tau Huang

IPC分类号： H01L21/02 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/331 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/8222

CPC分类号： H01L21/76843 ,  H01L21/02063 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76855 ,  H01L21/76867 ,  H01L21/7688

摘要： A process for fabricating interconnects is provided. First, a substrate having a dielectric layer and silicon-containing mask layer on the dielectric layer is provided. The dielectric layer is patterned to form an opening. Thereafter, a metallic glue layer is formed over the silicon-containing mask layer and the interior surfaces of the opening. A metallic layer is formed over the substrate to fill the opening and cover the metallic glue layer. A thermal treatment process is next carried out so that the metallic glue layer reacts with the silicon-containing mask layer to form a metal silicide layer. A portion of the metallic layer is removed to expose the metal silicide layer. A solution mixture containing hydrogen peroxide, sulfuric acid, water and hydrofluoric acid is used to remove the metal silicide layer. The silicon-containing mask layer is also removed to expose the dielectric layer. The solution mixture containing hydrogen peroxide, sulfuric acid, water and hydrofluoric acid can remove the metal silicide layer completely without damaging the metallic layer.

摘要翻译： 提供了制造互连的工艺。 首先，提供在电介质层上具有电介质层和含硅掩模层的基板。 将介电层图案化以形成开口。 此后，在含硅掩模层和开口的内表面上形成金属胶层。 金属层形成在衬底上以填充开口并覆盖金属胶层。 接下来进行热处理工艺，使得金属胶层与含硅掩模层反应形成金属硅化物层。 去除金属层的一部分以露出金属硅化物层。 使用含有过氧化氢，硫酸，水和氢氟酸的溶液混合物去除金属硅化物层。 还除去含硅掩模层以暴露介电层。 含有过氧化氢，硫酸，水和氢氟酸的溶液混合物可以完全去除金属硅化物层而不会损坏金属层。

公开(公告)号：US20050051191A1

公开(公告)日：2005-03-10

申请号：US10707081

申请日：2003-11-20

申请人： Shih-Chieh Kao ,  Jin-Tau Huang ,  Yi-Nan Chen

发明人： Shih-Chieh Kao ,  Jin-Tau Huang ,  Yi-Nan Chen

IPC分类号： B08B11/00 ,  H01L21/306 ,  H01L21/311 ,  H01L21/768

CPC分类号： H01L21/02063 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76838

摘要： A cleaning method used in the fabrication of metallic interconnects is provided. A substrate having a conductive layer and a dielectric layer on the conductive layer is provided. An opening is formed in the dielectric layer. The opening exposes a portion of the conductive layer. The opening is cleaned using a mixture containing sulfuric acid and hydrogen peroxide. In this invention, the mixture containing sulfuric acid and hydrogen peroxide provides an effective means of removing the residues within the opening so that the electrical conductivity of a subsequently formed contact is improved.

摘要翻译： 提供了用于制造金属互连件的清洁方法。 提供了在导电层上具有导电层和电介质层的衬底。 在电介质层中形成开口。 开口暴露导电层的一部分。 使用含有硫酸和过氧化氢的混合物清洁开口。 在本发明中，含有硫酸和过氧化氢的混合物提供了去除开口内残留物的有效手段，从而提高随后形成的触点的导电性。

公开(公告)号：US06881670B2

公开(公告)日：2005-04-19

申请号：US10709264

申请日：2004-04-26

申请人： Tien-Sung Chen ,  Yi-Nan Chen ,  Jin-Tau Huang

发明人： Tien-Sung Chen ,  Yi-Nan Chen ,  Jin-Tau Huang

IPC分类号： H01L21/02 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/331 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/8222

CPC分类号： H01L21/76843 ,  H01L21/02063 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76855 ,  H01L21/76867 ,  H01L21/7688

摘要： A process for fabricating interconnects is provided. First, a substrate having a dielectric layer and silicon-containing mask layer on the dielectric layer is provided. The dielectric layer is patterned to form an opening. Thereafter, a metallic glue layer is formed over the silicon-containing mask layer and the interior surfaces of the opening. A metallic layer is formed over the substrate to fill the opening and cover the metallic glue layer. A thermal treatment process is next carried out so that the metallic glue layer reacts with the silicon-containing mask layer to form a metal silicide layer. A portion of the metallic layer is removed to expose the metal silicide layer. A solution mixture containing hydrogen peroxide, sulfuric acid, water and hydrofluoric acid is used to remove the metal silicide layer. The silicon-containing mask layer is also removed to expose the dielectric layer. The solution mixture containing hydrogen peroxide, sulfuric acid, water and hydrofluoric acid can remove the metal silicide layer completely without damaging the metallic layer.

摘要翻译： 提供了制造互连的工艺。 首先，提供在电介质层上具有电介质层和含硅掩模层的基板。 将介电层图案化以形成开口。 此后，在含硅掩模层和开口的内表面上形成金属胶层。 金属层形成在衬底上以填充开口并覆盖金属胶层。 接下来进行热处理工艺，使得金属胶层与含硅掩模层反应形成金属硅化物层。 去除金属层的一部分以露出金属硅化物层。 使用含有过氧化氢，硫酸，水和氢氟酸的溶液混合物去除金属硅化物层。 还除去含硅掩模层以暴露介电层。 含有过氧化氢，硫酸，水和氢氟酸的溶液混合物可以完全去除金属硅化物层而不会损坏金属层。

公开(公告)号：US08963282B2

公开(公告)日：2015-02-24

申请号：US13231961

申请日：2011-09-14

申请人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L29/72 ,  H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56

CPC分类号： H01L23/562 ,  H01L21/311 ,  H01L21/561 ,  H01L21/76224 ,  H01L21/78 ,  H01L23/3178 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in a form of a grid to form a crack stop structure.

摘要翻译： 半导体结构包括矩阵，集成电路和划线。 矩阵包括划线区域和电路区域。 集成电路设置在电路区域内。 划痕线设置在划线区域内并且包括设置在矩阵中并且邻近电路区域的裂缝停止沟槽。 裂缝停止沟槽与电路区域的一侧平行，并填充有格栅形式的复合材料以形成裂纹停止结构。

公开(公告)号：US08692245B2

公开(公告)日：2014-04-08

申请号：US13214227

申请日：2011-08-21

申请人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L23/544 ,  H01L23/482 ,  H01L21/762

CPC分类号： H01L21/76224 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention in a first aspect proposes a semiconductor structure with a crack stop structure. The semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in the form of a grid to form a crack stop structure.

摘要翻译： 本发明在第一方面提出了一种具有裂纹停止结构的半导体结构。 半导体结构包括矩阵，集成电路和划线。 矩阵包括划线区域和电路区域。 集成电路设置在电路区域内。 划痕线设置在划线区域内并且包括设置在矩阵中并且邻近电路区域的裂缝停止沟槽。 裂缝停止沟槽与电路区域的一侧平行，并填充有格栅形式的复合材料以形成裂纹停止结构。

公开(公告)号：US20130062727A1

公开(公告)日：2013-03-14

申请号：US13231961

申请日：2011-09-14

申请人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L29/06 ,  H01L21/76

CPC分类号： H01L23/562 ,  H01L21/311 ,  H01L21/561 ,  H01L21/76224 ,  H01L21/78 ,  H01L23/3178 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in a form of a grid to form a crack stop structure.

摘要翻译： 半导体结构包括矩阵，集成电路和划线。 矩阵包括划线区域和电路区域。 集成电路设置在电路区域内。 划痕线设置在划线区域内并且包括设置在矩阵中并且邻近电路区域的裂缝停止沟槽。 裂缝停止沟槽与电路区域的一侧平行，并填充有格栅形式的复合材料以形成裂纹停止结构。

公开(公告)号：US06992393B2

公开(公告)日：2006-01-31

申请号：US10708848

申请日：2004-03-29

申请人： Tse-Yao Huang ,  Yi-Nan Chen ,  Chih-Ching Lin

发明人： Tse-Yao Huang ,  Yi-Nan Chen ,  Chih-Ching Lin

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/7685 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76837

摘要： A method for fabricating interconnects is provided. The method comprises forming a conducting line on a first dielectric layer; forming a first liner layer on the surfaces of the first dielectric layer and the conducting line; forming a second liner layer on the first liner layer; forming a second dielectric layer on the second liner layer, wherein the etching selectivity rate of the second dielectric layer is higher than the etching selectivity rate of the second liner; and patterning the second dielectric layer to form a contact window opening through the second liner layer and the first liner layer to expose the surface of the conducting line. Because the second dielectric layer having an etching rate higher than the etching rate of the second liner layer, the second liner layer can be used as an etch stop layer while patterning the second dielectric layer.

摘要翻译： 提供一种用于制造互连的方法。 该方法包括在第一电介质层上形成导线; 在所述第一介电层和所述导电线的表面上形成第一衬里层; 在所述第一衬里层上形成第二衬里层; 在所述第二衬里层上形成第二电介质层，其中所述第二电介质层的蚀刻选择率高于所述第二衬垫的蚀刻选择率; 以及图案化所述第二电介质层以形成穿过所述第二衬垫层和所述第一衬里层的接触窗口，以露出所述导电线的表面。 由于第二电介质层的蚀刻速率高于第二衬垫层的蚀刻速率，所以第二衬里层可以用作蚀刻停止层，同时构图第二介电层。