公开(公告)号：US08409947B2

公开(公告)日：2013-04-02

申请号：US12693080

申请日：2010-01-25

申请人： Jin-bum Kim ,  Wook-je Kim ,  Yu-gyun Shin ,  Kwan-heum Lee ,  Sun-ghil Lee

发明人： Jin-bum Kim ,  Wook-je Kim ,  Yu-gyun Shin ,  Kwan-heum Lee ,  Sun-ghil Lee

IPC分类号： H01L21/8238

CPC分类号： H01L29/7848 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

摘要： Provided is a simplified method of manufacturing a semiconductor device having a stress creating layer. A first conductive first impurity region is formed on a semiconductor substrate on both sides of a first gate of a first area of the semiconductor substrate, and a second conductive second impurity region is formed on the semiconductor substrate on both sides of a second gate of a second area. First and second spacers are formed on sidewalls of the first and second gates, respectively. First and second semiconductor layers are formed in portions of the semiconductor substrate so as to contact the first and second impurity regions, respectively. The second semiconductor layer is removed. First and second barrier layers are formed in the first and second contact holes of the insulation layer, respectively.

摘要翻译： 提供了一种制造具有应力产生层的半导体器件的简化方法。 在半导体衬底的第一区域的第一栅极的两侧上的半导体衬底上形成第一导电第一杂质区，并且在半导体衬底的第二栅极的两侧的半导体衬底上形成第二导电第二杂质区 第二区。 第一和第二间隔物分别形成在第一和第二栅极的侧壁上。 第一半导体层和第二半导体层分别形成在半导体衬底的部分中，以分别接触第一和第二杂质区。 去除第二半导体层。 第一和第二阻挡层分别形成在绝缘层的第一和第二接触孔中。

公开(公告)号：US08361860B2

公开(公告)日：2013-01-29

申请号：US12656130

申请日：2010-01-19

申请人： Jin-bum Kim ,  Wook-je Kim ,  Kwan-heum Lee ,  Yu-gyun Shin ,  Sun-ghil Lee

发明人： Jin-bum Kim ,  Wook-je Kim ,  Kwan-heum Lee ,  Yu-gyun Shin ,  Sun-ghil Lee

IPC分类号： H01L21/8242

CPC分类号： H01L21/7687 ,  H01L27/10855 ,  H01L28/91

摘要： A method of manufacturing a semiconductor device may include forming a first interlayer insulation layer on a substrate including at least one gate structure formed thereon, the substrate having a plurality of source/drain regions formed on both sides of the at least one gate structure, forming at least one buried contact plug on at least one of the plurality of source/drain regions and in the first interlayer insulation layer, forming a second interlayer insulation layer on the first interlayer insulation layer and the at least one buried contact plug, exposing the at least one buried contact plug in the second interlayer insulation layer by forming at least one contact hole, implanting ions in the at least one contact hole in order to create an amorphous upper portion of the at least one buried contact plug, depositing a lower electrode layer on the second interlayer insulation layer and the at least one contact hole, and forming a metal silicide layer in the amorphous upper portion of the at least one buried contact plug.

摘要翻译： 制造半导体器件的方法可以包括在包括形成在其上的至少一个栅极结构的衬底上形成第一层间绝缘层，所述衬底具有形成在所述至少一个栅极结构的两侧上的多个源/漏区，形成 在所述多个源极/漏极区域和所述第一层间绝缘层中的至少一个上的至少一个埋置的接触插塞，在所述第一层间绝缘层和所述至少一个埋置的接触插塞上形成第二层间绝缘层， 通过形成至少一个接触孔，在所述至少一个接触孔中注入离子，以形成所述至少一个埋入接触插塞的非晶体上部，沉积下部电极层 在所述第二层间绝缘层和所述至少一个接触孔上，并且在所述非晶体上部形成金属硅化物层 的所述至少一个埋入式接触插塞。

公开(公告)号：US20100197092A1

公开(公告)日：2010-08-05

申请号：US12693080

申请日：2010-01-25

申请人： Jin-bum Kim ,  Wook-je Kim ,  Yu-gyun Shin ,  Kwan-heum Lee ,  Sun-Ghil Lee

发明人： Jin-bum Kim ,  Wook-je Kim ,  Yu-gyun Shin ,  Kwan-heum Lee ,  Sun-Ghil Lee

IPC分类号： H01L21/8238 ,  H01L21/20

CPC分类号： H01L29/7848 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

摘要： Provided is a simplified method of manufacturing a semiconductor device having a stress creating layer. A first conductive first impurity region is formed on a semiconductor substrate on both sides of a first gate of a first area of the semiconductor substrate, and a second conductive second impurity region is formed on the semiconductor substrate on both sides of a second gate of a second area. First and second spacers are formed on sidewalls of the first and second gates, respectively. First and second semiconductor layers are formed in portions of the semiconductor substrate so as to contact the first and second impurity regions, respectively. The second semiconductor layer is removed. First and second barrier layers are formed in the first and second contact holes of the insulation layer, respectively.

摘要翻译： 提供了一种制造具有应力产生层的半导体器件的简化方法。 在半导体衬底的第一区域的第一栅极的两侧上的半导体衬底上形成第一导电第一杂质区，并且在半导体衬底的第二栅极的两侧的半导体衬底上形成第二导电第二杂质区 第二区。 第一和第二间隔物分别形成在第一和第二栅极的侧壁上。 第一半导体层和第二半导体层分别形成在半导体衬底的部分中，以分别接触第一和第二杂质区。 去除第二半导体层。 第一和第二阻挡层分别形成在绝缘层的第一和第二接触孔中。

公开(公告)号：US20100330758A1

公开(公告)日：2010-12-30

申请号：US12656130

申请日：2010-01-19

申请人： Jin-bum Kim ,  Wook-je Kim ,  Kwan-heum Lee ,  Yu-gyun Shin ,  Sun-ghil Lee

发明人： Jin-bum Kim ,  Wook-je Kim ,  Kwan-heum Lee ,  Yu-gyun Shin ,  Sun-ghil Lee

IPC分类号： H01L21/8242 ,  H01L21/283

CPC分类号： H01L21/7687 ,  H01L27/10855 ,  H01L28/91

摘要： A method of manufacturing a semiconductor device may include forming a first interlayer insulation layer on a substrate including at least one gate structure formed thereon, the substrate having a plurality of source/drain regions formed on both sides of the at least one gate structure, forming at least one buried contact plug on at least one of the plurality of source/drain regions and in the first interlayer insulation layer, forming a second interlayer insulation layer on the first interlayer insulation layer and the at least one buried contact plug, exposing the at least one buried contact plug in the second interlayer insulation layer by forming at least one contact hole, implanting ions in the at least one contact hole in order to create an amorphous upper portion of the at least one buried contact plug, depositing a lower electrode layer on the second interlayer insulation layer and the at least one contact hole, and forming a metal silicide layer in the amorphous upper portion of the at least one buried contact plug.

摘要翻译： 制造半导体器件的方法可以包括在包括形成在其上的至少一个栅极结构的衬底上形成第一层间绝缘层，所述衬底具有形成在所述至少一个栅极结构的两侧上的多个源/漏区，形成 在所述多个源极/漏极区域和所述第一层间绝缘层中的至少一个上的至少一个埋置的接触插塞，在所述第一层间绝缘层和所述至少一个埋置的接触插塞上形成第二层间绝缘层， 通过形成至少一个接触孔，在所述至少一个接触孔中注入离子，以形成所述至少一个埋入接触插塞的非晶体上部，沉积下部电极层 在所述第二层间绝缘层和所述至少一个接触孔上，并且在所述非晶体上部形成金属硅化物层 的所述至少一个埋入式接触插塞。

公开(公告)号：US20060027875A1

公开(公告)日：2006-02-09

申请号：US11249096

申请日：2005-10-11

申请人： Chang-Huhn Lee ,  Mun-Mo Jeong ,  Wook-je Kim

发明人： Chang-Huhn Lee ,  Mun-Mo Jeong ,  Wook-je Kim

IPC分类号： H01L29/94 ,  H01L29/76 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/6656 ,  H01L21/823468 ,  Y10S257/90 ,  Y10S438/978

摘要： Embodiments of the invention provide a semiconductor device and a fabrication method for a semiconductor device that includes the processes of forming multiple gates on a silicon substrate, forming a gate spacer having a positive slope at the gate spacer edge, depositing a polysilicon layer on the silicon substrate between the gates, etching a portion of the polysilicon layer to form an opening exposing a portion of the silicon substrate, and forming an inter-insulation layer to the exposed portion of the silicon substrate to fill the opening. Using an annealing process applied to a layer in the gate spacer, the etch selectivity can be selectively controlled and consequently, the degree of slope at the gate spacer edge is predetermined.

摘要翻译： 本发明的实施例提供一种用于半导体器件的半导体器件和制造方法，其包括在硅衬底上形成多个栅极的工艺，在栅极间隔物边缘处形成具有正斜率的栅极间隔物，在硅上沉积多晶硅层 蚀刻多晶硅层的一部分以形成露出硅衬底的一部分的开口，以及形成绝缘层到硅衬底的暴露部分以填充开口。 使用施加到栅极间隔物中的层的退火工艺，可以选择性地控制蚀刻选择性，因此预定栅极间隔物边缘处的斜率。

公开(公告)号：US06969673B2

公开(公告)日：2005-11-29

申请号：US10631456

申请日：2003-07-30

申请人： Chang-Huhn Lee ,  Mun-Mo Jeong ,  Wook-je Kim

发明人： Chang-Huhn Lee ,  Mun-Mo Jeong ,  Wook-je Kim

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/3205

CPC分类号： H01L29/6656 ,  H01L21/823468 ,  Y10S257/90 ,  Y10S438/978

摘要： Embodiments of the invention provide a semiconductor device and a fabrication method for a semiconductor device that includes the processes of forming multiple gates on a silicon substrate, forming a gate spacer having a positive slope at the gate spacer edge, depositing a polysilicon layer on the silicon substrate between the gates, etching a portion of the polysilicon layer to form an opening exposing a portion of the silicon substrate, and forming an inter-insulation layer to the exposed portion of the silicon substrate to fill the opening. Using an annealing process applied to a layer in the gate spacer, the etch selectivity can be selectively controlled and consequently, the degree of slope at the gate spacer edge is predetermined.

摘要翻译： 本发明的实施例提供一种用于半导体器件的半导体器件和制造方法，其包括在硅衬底上形成多个栅极的工艺，在栅极间隔物边缘处形成具有正斜率的栅极间隔物，在硅上沉积多晶硅层 蚀刻多晶硅层的一部分以形成露出硅衬底的一部分的开口，以及形成绝缘层到硅衬底的暴露部分以填充开口。 使用施加到栅极间隔物中的层的退火工艺，可以选择性地控制蚀刻选择性，因此预定栅极间隔物边缘处的斜率。

公开(公告)号：US07566924B2

公开(公告)日：2009-07-28

申请号：US11249096

申请日：2005-10-11

申请人： Chang-Huhn Lee ,  Mun-Mo Jeong ,  Wook-je Kim

发明人： Chang-Huhn Lee ,  Mun-Mo Jeong ,  Wook-je Kim

IPC分类号： H01L31/112

CPC分类号： H01L29/6656 ,  H01L21/823468 ,  Y10S257/90 ,  Y10S438/978

摘要： Embodiments of the invention provide a semiconductor device and a fabrication method for a semiconductor device that includes the processes of forming multiple gates on a silicon substrate, forming a gate spacer having a positive slope at the gate spacer edge, depositing a polysilicon layer on the silicon substrate between the gates, etching a portion of the polysilicon layer to form an opening exposing a portion of the silicon substrate, and forming an inter-insulation layer to the exposed portion of the silicon substrate to fill the opening. Using an annealing process applied to a layer in the gate spacer, the etch selectivity can be selectively controlled and consequently, the degree of slope at the gate spacer edge is predetermined.

摘要翻译： 本发明的实施例提供一种用于半导体器件的半导体器件和制造方法，其包括在硅衬底上形成多个栅极的工艺，在栅极间隔物边缘处形成具有正斜率的栅极间隔物，在硅上沉积多晶硅层 蚀刻多晶硅层的一部分以形成露出硅衬底的一部分的开口，以及形成绝缘层到硅衬底的暴露部分以填充开口。 使用施加到栅极间隔物中的层的退火工艺，可以选择性地控制蚀刻选择性，因此预定栅极间隔物边缘处的斜率。

公开(公告)号：US20060046370A1

公开(公告)日：2006-03-02

申请号：US11210820

申请日：2005-08-25

申请人： Yong-chul Oh ,  Wook-je Kim ,  Dong-gun Park ,  Woun-suck Yang

发明人： Yong-chul Oh ,  Wook-je Kim ,  Dong-gun Park ,  Woun-suck Yang

IPC分类号： H01L21/8238 ,  H01L21/425 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/28035 ,  H01L21/28061 ,  H01L21/3212 ,  H01L21/823842

摘要： A method of manufacturing a MOS transistor with a void-free gate electrode is provided. A gate oxide film may be formed on a semiconductor, and a poly silicon film for a gate electrode may be deposited on the gate oxide film. P-type impurities may be implanted into the poly silicon film, and a thickness of the poly silicon film may be removed by chemical mechanical polishing.

摘要翻译： 提供一种制造具有无空隙栅电极的MOS晶体管的方法。 可以在半导体上形成栅极氧化膜，并且可以在栅极氧化膜上沉积用于栅电极的多晶硅膜。 可以将P型杂质注入到多晶硅膜中，并且可以通过化学机械抛光去除多晶硅膜的厚度。

公开(公告)号：US07303955B2

公开(公告)日：2007-12-04

申请号：US11300233

申请日：2005-12-14

申请人： Wook-je Kim

发明人： Wook-je Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/7843 ,  H01L21/76801 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76897 ,  H01L21/823871 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/6656

摘要： In a semiconductor memory device with a high operating current and a method of manufacturing the same, a semiconductor substrate is formed in which a memory cell region and a peripheral circuit region including an N-channel metal oxide semiconductor (NMOS) region and a P-channel metal oxide semiconductor (PMOS) region are defined. A gate electrode with sidewall spacers is formed in each of the memory cell region and the peripheral circuit region. Source and drain regions are formed in the semiconductor substrate at sides of the gate electrode to form metal oxide semiconductor (MOS) transistors. A first etch stop layer is formed on the semiconductor substrate where the MOS transistors are formed. A second etch stop layer is selectively formed in the NMOS region of the peripheral circuit region.

摘要翻译： 在具有高工作电流的半导体存储器件及其制造方法中，形成半导体衬底，其中存储单元区域和包括N沟道金属氧化物半导体（NMOS）区域和P-沟道金属氧化物半导体区域的外围电路区域， 沟道金属氧化物半导体（PMOS）区域。 在每个存储单元区域和外围电路区域中形成具有侧壁间隔物的栅电极。 源极和漏极区域形成在栅极侧的半导体衬底中，以形成金属氧化物半导体（MOS）晶体管。 在形成MOS晶体管的半导体衬底上形成第一蚀刻停止层。 在外围电路区域的NMOS区域中选择性地形成第二蚀刻停止层。

公开(公告)号：US20060189085A1

公开(公告)日：2006-08-24

申请号：US11356998

申请日：2006-02-17

申请人： Wook-je Kim ,  Yong-chul Oh

发明人： Wook-je Kim ,  Yong-chul Oh

IPC分类号： H01L21/336

CPC分类号： H01L21/823835 ,  H01L21/28061 ,  H01L21/823842

摘要： In a method of forming a dual polysilicon gate of a semiconductor device, a polysilicon layer is formed on a substrate divided into an NMOS region and a PMOS region. Then, a p-type impurity is implanted in the PMOS region. A thermal annealing process is performed that causes generation of a compound material at a top surface of the polysilicon layer in the PMOS region as a result of bonding between the p-type impurity and the polysilicon layer. A cleaning process is then performed. During the cleaning process, the compound material decreases an etch rate in the PMOS region, so that a height of the polysilicon layer in the NMOS region is reduced relative to that of the polysilicon layer in the PMOS region. Accordingly, an intended range of a threshold voltage can be obtained by blocking the p-type impurity in the PMOS region from penetrating into a gate insulation layer. Also, by maintaining an increased height of a gate transmission material in the cell region, a resistance increase is thereby prevented.

摘要翻译： 在形成半导体器件的双重多晶硅栅极的方法中，在分成NMOS区域和PMOS区域的衬底上形成多晶硅层。 然后，在PMOS区域中注入p型杂质。 由于p型杂质和多晶硅层之间的结合，进行了在PMOS区域中的多晶硅层的顶面产生复合材料的热退火处理。 然后执行清洁处理。 在清洁过程中，复合材料降低了PMOS区域中的蚀刻速率，使得NMOS区域中的多晶硅层的高度相对于PMOS区域中的多晶硅层的高度减小。 因此，可以通过阻塞PMOS区中的p型杂质渗透到栅极绝缘层中来获得阈值电压的期望范围。 此外，通过保持电池区域中的栅极传输材料的高度增加，由此防止了电阻增加。