公开(公告)号：US20120204141A1

公开(公告)日：2012-08-09

申请号：US13449732

申请日：2012-04-18

申请人： Jinwoo Choi ,  Sungjun Chun ,  Anand Haridass ,  Roger Weekly

发明人： Jinwoo Choi ,  Sungjun Chun ,  Anand Haridass ,  Roger Weekly

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5036 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0219 ,  H05K1/0224 ,  H05K3/4629 ,  H05K2201/09236 ,  H05K2201/09681 ,  H01L2924/00

摘要： A method reduces coupling noise and controls impedance discontinuity in ceramic packages by: providing at least one reference mesh layer; providing a plurality of signal trace layers, with each signal layer having one or more signal lines and the reference mesh layer being adjacent to one or more of the signal layers; disposing a plurality of vias through the at least one reference mesh layer, with each via providing a voltage (Vdd) power connection or a ground (Gnd) connection; selectively placing via-connected coplanar-type shield (VCS) lines relative to the signal lines, with a first VCS line extended along a first side of a first signal line and a second VCS line extended along a second, opposing side of said first signal line. Each of the VCS lines interconnect with and extend past one or more vias located within a directional path along which the VCS lines extends.

摘要翻译： 一种方法通过以下方式减少耦合噪声并控制陶瓷封装中的阻抗不连续性：提供至少一个参考网格层; 提供多个信号迹线层，其中每个信号层具有一个或多个信号线，并且所述参考网格层与所述信号层中的一个或多个相邻; 通过所述至少一个参考网格层布置多个通孔，其中每个通孔提供电压（Vdd）电源连接或接地（Gnd）连接; 选择性地将通过连接的共面型屏蔽（VCS）线相对于信号线放置，其中第一VCS线沿着第一信号线的第一侧延伸，并且第二VCS线沿着所述第一信号的第二相对侧延伸 线。 VCS线路中的每一条与位于VCS线延伸的定向路径内的一个或多个通孔相互连接并延伸。

公开(公告)号：US08645889B2

公开(公告)日：2014-02-04

申请号：US13449732

申请日：2012-04-18

申请人： Jinwoo Choi ,  Sungjun Chun ,  Anand Haridass ,  Roger Weekly

发明人： Jinwoo Choi ,  Sungjun Chun ,  Anand Haridass ,  Roger Weekly

IPC分类号： G06F17/50 ,  H05K1/00

CPC分类号： G06F17/5068 ,  G06F17/5036 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0219 ,  H05K1/0224 ,  H05K3/4629 ,  H05K2201/09236 ,  H05K2201/09681 ,  H01L2924/00

摘要： A method reduces coupling noise and controls impedance discontinuity in ceramic packages by: providing at least one reference mesh layer; providing a plurality of signal trace layers, with each signal layer having one or more signal lines and the reference mesh layer being adjacent to one or more of the signal layers; disposing a plurality of vias through the at least one reference mesh layer, with each via providing a voltage (Vdd) power connection or a ground (Gnd) connection; selectively placing via-connected coplanar-type shield (VCS) lines relative to the signal lines, with a first VCS line extended along a first side of a first signal line and a second VCS line extended along a second, opposing side of said first signal line. Each of the VCS lines interconnect with and extend past one or more vias located within a directional path along which the VCS lines extends.

摘要翻译： 一种方法通过以下方式减少耦合噪声并控制陶瓷封装中的阻抗不连续性：提供至少一个参考网格层; 提供多个信号迹线层，其中每个信号层具有一个或多个信号线，并且所述参考网格层与所述信号层中的一个或多个相邻; 通过所述至少一个参考网格层布置多个通孔，其中每个通孔提供电压（Vdd）电源连接或接地（Gnd）连接; 选择性地将通过连接的共面型屏蔽（VCS）线相对于信号线放置，其中第一VCS线沿着第一信号线的第一侧延伸，并且第二VCS线沿着所述第一信号的第二相对侧延伸 线。 VCS线路中的每一条与位于VCS线延伸的定向路径内的一个或多个通孔相互连接并延伸。

公开(公告)号：US08288657B2

公开(公告)日：2012-10-16

申请号：US12577259

申请日：2009-10-12

申请人： Jinwoo Choi ,  Sungjun Chun ,  Anand Haridass ,  Roger Weekly

发明人： Jinwoo Choi ,  Sungjun Chun ,  Anand Haridass ,  Roger Weekly

IPC分类号： H05K1/00

CPC分类号： G06F17/5068 ,  G06F17/5036 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0219 ,  H05K1/0224 ,  H05K3/4629 ,  H05K2201/09236 ,  H05K2201/09681 ,  H01L2924/00

摘要： An improved multi-layered ceramic package comprises: a plurality of signal layers, each having one or more signal lines; a plurality of vias, each providing one of a voltage (Vdd) power connection or a ground (Gnd) connection; at least one reference mesh layer adjacent to one or more signal layers; and a plurality of via-connected coplanar-type shield (VCS) lines, with a first VCS line extending on a first side of a first signal line within the plurality of signal layers and a second VCS line extending on a second opposing side of the first signal line. Each of the plurality of VCS lines interconnect with and extend past one or more vias that are located along the directional path in which the VCS lines runs. The placement of the VCS lines relative to the signal lines reduces coupling noise and controls impedance discontinuity in the ceramic package.

摘要翻译： 一种改进的多层陶瓷封装包括：多个信号层，每个具有一个或多个信号线; 多个通孔，每个通孔提供电压（Vdd）电源连接或地（Gnd）连接中的一个; 与一个或多个信号层相邻的至少一个参考网格层; 以及多个通孔连接的共面型屏蔽（VCS）线，其中在所述多个信号层中的第一信号线的第一侧上延伸的第一VCS线和在所述多个信号层的第二相对侧上延伸的第二VCS线 第一条信号线。 多个VCS线路中的每一条与VCS线路运行的定向路径相互连接并延伸经过一个或多个通孔。 VCS线相对于信号线的放置减少了耦合噪声并且控制了陶瓷封装中的阻抗不连续性。

公开(公告)号：US20110083888A1

公开(公告)日：2011-04-14

申请号：US12577259

申请日：2009-10-12

申请人： Jinwoo Choi ,  Sungjun Chun ,  Anand Haridass ,  Roger Weekly

发明人： Jinwoo Choi ,  Sungjun Chun ,  Anand Haridass ,  Roger Weekly

IPC分类号： H05K1/02 ,  H05K3/10 ,  G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5036 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0219 ,  H05K1/0224 ,  H05K3/4629 ,  H05K2201/09236 ,  H05K2201/09681 ,  H01L2924/00

摘要： An improved multi-layered ceramic package comprises: a plurality of signal layers, each having one or more signal lines; a plurality of vias, each providing one of a voltage (Vdd) power connection or a ground (Gnd) connection; at least one reference mesh layer adjacent to one or more signal layers; and a plurality of via-connected coplanar-type shield (VCS) lines, with a first VCS line extending on a first side of a first signal line within the plurality of signal layers and a second VCS line extending on a second opposing side of the first signal line. Each of the plurality of VCS lines interconnect with and extend past one or more vias that are located along the directional path in which the VCS lines runs. The placement of the VCS lines relative to the signal lines reduces coupling noise and controls impedance discontinuity in the ceramic package.

摘要翻译： 一种改进的多层陶瓷封装包括：多个信号层，每个具有一个或多个信号线; 多个通孔，每个通孔提供电压（Vdd）电源连接或地（Gnd）连接中的一个; 与一个或多个信号层相邻的至少一个参考网格层; 以及多个通孔连接的共面型屏蔽（VCS）线，其中在所述多个信号层中的第一信号线的第一侧上延伸的第一VCS线和在所述多个信号层的第二相对侧上延伸的第二VCS线 第一条信号线。 多个VCS线路中的每一条与VCS线路运行的定向路径相互连接并延伸经过一个或多个通孔。 VCS线相对于信号线的放置减少了耦合噪声并且控制了陶瓷封装中的阻抗不连续性。

公开(公告)号：US20080087457A1

公开(公告)日：2008-04-17

申请号：US11951646

申请日：2007-12-06

申请人： Anand Haridass ,  Andreas Huber ,  Bao Truong ,  Roger Weekly

发明人： Anand Haridass ,  Andreas Huber ,  Bao Truong ,  Roger Weekly

IPC分类号： H05K7/06

CPC分类号： H01L23/50 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  Y10T29/49155 ,  Y10T29/49163 ,  H01L2924/00

摘要： A mechanism for reducing the vertical cross-talk interference experienced in signal lines due to the inductive affects from signal lines in other signal planes of a multi-layer ceramic package is provided. With the apparatus and method, one or more vias in the multi-layer ceramic package may be removed from the structure to provide area through which an offset of the signal lines may pass. Because these offsets of the signal lines exist in parallel planes above or below each other, with no ground lines existing directly between these signal line offsets, a capacitive cross-talk is introduced into the signal lines. This capacitive cross-talk is opposite in polarity to the inductive cross-talk already experienced by the signal lines. As a result, the capacitive cross-talk tends to negate or reduce the inductive cross-talk thereby reducing the far end noise in the signal line.

公开(公告)号：US20070250796A1

公开(公告)日：2007-10-25

申请号：US11379446

申请日：2006-04-20

申请人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Roger Weekly

发明人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Roger Weekly

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/78 ,  Y02E60/76 ,  Y04S40/22

摘要： A method for designing a power distribution system including: receiving a cross section file that contains the layout of a PCB including a location of one or more power sinks and sources on the PCB; creating an initial power distribution system; evaluating the initial power distribution system against a cost function; creating a new power distribution system; evaluating the new power distribution system against the cost function; determining if the cost function associated with the new power distribution system is equal to or greater than a stop criterion; and creating another new power distribution system if the cost function associated with the new power distribution system is greater than the stop criterion.

摘要翻译： 一种用于设计配电系统的方法，包括：接收包含PCB的布局的横截面文件，所述布局包括PCB上的一个或多个电源和源的位置; 创建初始配电系统; 根据成本函数评估初始配电系统; 建立新的配电系统; 根据成本函数评估新的配电系统; 确定与新配电系统相关联的成本函数是否等于或大于停止准则; 并且如果与新配电系统相关联的成本函数大于停止标准，则创建另一新的配电系统。

公开(公告)号：US20080092101A1

公开(公告)日：2008-04-17

申请号：US11951705

申请日：2007-12-06

申请人： Anand Haridass ,  Andreas Huber ,  Bao Truong ,  Roger Weekly

发明人： Anand Haridass ,  Andreas Huber ,  Bao Truong ,  Roger Weekly

IPC分类号： G06F17/50

CPC分类号： H01L23/50 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  Y10T29/49155 ,  Y10T29/49163 ,  H01L2924/00

摘要： A mechanism for reducing the vertical cross-talk interference experienced in signal lines due to the inductive affects from signal lines in other signal planes of a multi-layer ceramic package is provided. With the apparatus and method, one or more vias in the multi-layer ceramic package may be removed from the structure to provide area through which an offset of the signal lines may pass. Because these offsets of the signal lines exist in parallel planes above or below each other, with no ground lines existing directly between these signal line offsets, a capacitive cross-talk is introduced into the signal lines. This capacitive cross-talk is opposite in polarity to the inductive cross-talk already experienced by the signal lines. As a result, the capacitive cross-talk tends to negate or reduce the inductive cross-talk thereby reducing the far end noise in the signal line.

摘要翻译： 提供了一种用于减少由于来自多层陶瓷封装的其它信号面中的信号线的感应影响而在信号线中遭受的垂直串扰干扰的机制。 利用该装置和方法，多层陶瓷封装中的一个或多个通孔可以从结构中移除以提供信号线的偏移通过的区域。 由于信号线的这些偏移存在于彼此之上或之下的并行平面中，在这些信号线偏移之间没有直接存在接地线，所以在信号线中引入电容性串扰。 该电容串扰与信号线已经经历的电感串扰的极性相反。 结果，电容串扰倾向于消除或减少电感串扰，从而减少信号线中的远端噪声。

公开(公告)号：US20070260444A1

公开(公告)日：2007-11-08

申请号：US11380058

申请日：2006-04-25

申请人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm O'Reilly ,  Bao Gia-Harvey Truong ,  Roger Weekly

发明人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm O'Reilly ,  Bao Gia-Harvey Truong ,  Roger Weekly

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method of power delivery analysis and design for a hierarchical system including building a model corresponding to each element of the hierarchical system, compiling a repository that contains the models corresponding to each element of the hierarchical system, assembling a system model from the models contained in the repository, flattening the system model, and running a simulation on the flattened system model.

摘要翻译： 一种用于分层系统的功率传递分析和设计的方法，包括构建与分层系统的每个元件相对应的模型，编译包含与分层系统的每个元件相对应的模型的存储库，从包含的模型组装系统模型 存储库，平整系统模型，并在平面化系统模型上运行仿真。

公开(公告)号：US20070239387A1

公开(公告)日：2007-10-11

申请号：US11278848

申请日：2006-04-06

申请人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm O'Reilly ,  Bao Truong ,  Roger Weekly

发明人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm O'Reilly ,  Bao Truong ,  Roger Weekly

IPC分类号： G06F19/00

CPC分类号： G01R19/16552

摘要： An apparatus and method are provided for monitoring the voltage available in each domain of multiple voltage domains of a partitioned electronic chip. In embodiments of the invention, only a single pair of C4 pins is required for all voltage monitoring activity. One useful embodiment is directed to apparatus for monitoring the level of voltage associated with each domain in a partitioned chip. The apparatus comprises a single conductive link coupled to the chip, and further comprises a domain selection network having a single output and a plurality of switchable inputs, the output being connected to the single conductive link, and two inputs being connected to monitor respective voltage levels of two of the plurality of voltage domains. A control mechanism is disposed to operate the selection network, in order to selectively connect one of the inputs to the single conductive link, and a sensor device external to the electronic chip is connected to measure the monitored respective voltage levels of two of the plurality of voltage domains using the single conductive link.

摘要翻译： 提供了一种用于监视分区电子芯片的多个电压域的每个域中可用电压的装置和方法。 在本发明的实施例中，对于所有电压监视活动，仅需要一对C4引脚。 一个有用的实施例涉及用于监视与分区芯片中的每个域相关联的电压电平的装置。 该装置包括耦合到芯片的单个导电链路，并且还包括具有单个输出和多个可切换输入的域选择网络，该输出连接到单个导电链路，并且两个输入端被连接以监视相应的电压电平 的多个电压域中的两个。 设置控制机构以操作选择网络，以便选择性地将输入中的一个连接到单个导电链路，并且电子芯片外部的传感器装置被连接以测量所监视的相应的多个 电压域使用单个导电链路。

公开(公告)号：US20060272851A1

公开(公告)日：2006-12-07

申请号：US11146441

申请日：2005-06-06

申请人： Anand Haridass ,  Andreas Huber ,  Bao Truong ,  Roger Weekly

发明人： Anand Haridass ,  Andreas Huber ,  Bao Truong ,  Roger Weekly

IPC分类号： H05K7/06

CPC分类号： H01L23/50 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  Y10T29/49155 ,  Y10T29/49163 ,  H01L2924/00

摘要： A mechanism for reducing the vertical cross-talk interference experienced in signal lines due to the inductive affects from signal lines in other signal planes of a multi-layer ceramic package is provided. With the apparatus and method, one or more vias in the multi-layer ceramic package may be removed from the structure to provide area through which an offset of the signal lines may pass. Because these offsets of the signal lines exist in parallel planes above or below each other, with no ground lines existing directly between these signal line offsets, a capacitive cross-talk is introduced into the signal lines. This capacitive cross-talk is opposite in polarity to the inductive cross-talk already experienced by the signal lines. As a result, the capacitive cross-talk tends to negate or reduce the inductive cross-talk thereby reducing the far end noise in the signal line.

摘要翻译： 提供了一种用于减少由于来自多层陶瓷封装的其它信号面中的信号线的感应影响而在信号线中遭受的垂直串扰干扰的机制。 利用该装置和方法，多层陶瓷封装中的一个或多个通孔可以从结构中移除以提供信号线偏移通过的区域。 由于信号线的这些偏移存在于彼此之上或之下的并行平面中，在这些信号线偏移之间没有直接存在接地线，所以在信号线中引入电容性串扰。 该电容串扰与信号线已经经历的电感串扰的极性相反。 结果，电容串扰倾向于消除或减少电感串扰，从而减少信号线中的远端噪声。