公开(公告)号：US07027796B1

公开(公告)日：2006-04-11

申请号：US09888108

申请日：2001-06-22

申请人： Joel B. Linsky ,  Lars G. Jansson ,  Mark V. Lane

发明人： Joel B. Linsky ,  Lars G. Jansson ,  Mark V. Lane

IPC分类号： H04B1/16

CPC分类号： H03L7/193 ,  H03L7/10 ,  H03L2207/06

摘要： A frequency synthesizer device with a fast off-to-lock time to enable intermittent operation and achieve power savings through automatic control of its On/Off sequence.A relatively fast off-to-lock time is achieved by controlling the sequence of how various components of the synthesizer are reactivated. The voltage controlled oscillator is reactivated, at first operating at its previous operating frequency prior to being deactivated. The phase frequency detector is inhibited while its input signals, a reference signal and a feedback signal, are activated. In a channel hopping communication scheme, the phase frequency detector coarsely tunes the synthesizer to its previous operating frequency, and then jumps to its new operating frequency. Another aspect of the invention provides improved channel locking by guaranteeing that the phase of the feedback signal in a phase lock loop initially lags the phase of the reference frequency signal at the phase frequency detector.

摘要翻译： 频率合成器具有快速关断时间，可通过自动控制其On / Off序列实现间歇运行并实现功率节省。 通过控制合成器的各种组件如何重新启动的顺序来实现相对快速的非锁定时间。 压控振荡器被重新激活，首先在被禁用之前以其先前的工作频率工作。 当其输入信号，参考信号和反馈信号被激活时，相位频率检测器被禁止。 在频道跳频通信方案中，相位频率检测器将合成器粗调调谐到其先前的工作频率，然后跳到新的工作频率。 本发明的另一方面通过保证相位锁定回路中的反馈信号的相位最初滞后于相位频率检测器处的​​参考频率信号的相位来提供改进的通道锁定。

公开(公告)号：US5013941A

公开(公告)日：1991-05-07

申请号：US395259

申请日：1989-08-17

申请人： Lars G. Jansson

发明人： Lars G. Jansson

IPC分类号： G06F3/00 ,  H03K19/003 ,  H03K19/018

CPC分类号： H03K19/01812 ,  H03K19/00376

摘要： A translator-translator logic (TTL) to emitter coupled logic or current mode logic (ECL/CML) input buffer and translator circuit provides temperature compensated input and threshold signal voltage levels to a translator circuit ECL gate for improved operation of the translator circuit. A threshold clamp circuit is coupled between an on-chip band-gap bias generator and the base node of the reference transistor element of the translator circuit ECL gate. The threshold clamp circuit maintains a substantially fixed temperature compensated reference voltage or threshold voltage level at the base node of the reference transistor element, referenced to the temperature compensated current source voltage level V.sub.cs from the bias generator. An input clamp circuit also references the logic high signal voltage level V.sub.TH at the base node of the ECL gate input transistor element to V.sub.CS.

公开(公告)号：US4988899A

公开(公告)日：1991-01-29

申请号：US450826

申请日：1989-12-11

申请人： Lars G. Jansson

发明人： Lars G. Jansson

IPC分类号： H03K19/013 ,  H03K19/018

CPC分类号： H03K19/013 ,  H03K19/01806 ,  H03K19/01812

摘要： An ECL/CML to TTL translator circuit couples the output of an ECL/CML gate to the input of a TTL gate. The ECL/CML gate operates with reference to a first power rail higher reference voltage level with transistor elements operating in the non-saturation operating region. The TTL gate operates with reference to a second power rail lower reference voltage level with transistor elements operating in the saturation threshold operating region. The translator circuit includes a reference voltage level shifting constant current non-switching current mirror circuit coupled to the output of the ECL/CML gate for shifting the reference voltage level of the ECL/CML gate output from the higher reference voltage level to the lower reference voltage level. An operating region translating emitter follower output buffer circuit is coupled to receive the voltage level shifted output signal and drive the input of the TTL gate. The circuit functions of reference voltage level shifting and of operating region translating are thereby separated. Base drive to the phase splitter transistor element is limited by a base drive limiting anti-saturation clamp circuit. More generally, an overdrive and anti-saturation clamp control circuit provides high speed switching of a phase splitter transistor element, pulldown transistor element, or other TTL switching transistor element for generalized application in TTL internal and output gates and buffers. The overdrive and clamp control circuit provides a "programmable" base-collector clamp voltage for operation of TTL switching transistor elements in "soft" saturation, in threshold saturation, or entirely out of saturation for operation of linear TTL circuits.

摘要翻译： ECL / CML到TTL转换器电路将ECL / CML门的输出耦合到TTL门的输入。 ECL / CML门电路参考第一个电源轨更高的参考电压电平，晶体管元件工作在非饱和工作区域。 TTL栅极参考第二电源轨下参考电压电平工作，晶体管元件工作在饱和阈值工作区域。 转换器电路包括耦合到ECL / CML门的输出的参考电压电平移动恒流非开关电流镜电路，用于将ECL / CML门输出的参考电压电平从较高的参考电压电平移位到较低的参考电压 电压电平。 操作区域转换射极跟随器输出缓冲器电路被耦合以接收电压电平移位的输出信号并驱动TTL门的输入。 因此，参考电压电平转换和操作区域平移的电路功能被分离。 通过基极驱动限制抗饱和钳位电路来限制对分相器晶体管元件的基极驱动。 更一般地，过驱动和抗饱和钳位控制电路提供了用于TTL内部和输出门和缓冲器中广泛应用的相分离器晶体管元件，下拉晶体管元件或其它TTL开关晶体管元件的高速开关。 过驱动和钳位控制电路提供了一个“可编程的”集电极钳位电压，用于在“软”饱和，阈值饱和或完全在饱和状态下操作TTL线路TTL电路的TTL开关晶体管元件。

公开(公告)号：US5034632A

公开(公告)日：1991-07-23

申请号：US540641

申请日：1990-06-19

申请人： Lars G. Jansson ,  Michael G. Ward

发明人： Lars G. Jansson ,  Michael G. Ward

IPC分类号： H03K19/003 ,  H03K19/013 ,  H03K19/088

CPC分类号： H03K19/013 ,  H03K19/00376

摘要： A non-inverting TTL buffer circuit provides an input for receiving data signals at high and low potential levels and an output for transmitting data signals in phase with the input. The base node of an emitter follower transistor element is coupled to a collector node of the input transistor circuit in an inverting coupling. The emitter node is coupled to a base node of the phase splitter transistor element for sourcing base driven current to the phase splitter transistor element in response to data signals at the input. The emitter follower provides transient "overdrive" for fast turn on of the phase splitter. A first clamp circuit between the base node of the emitter follower transistor element and the low potential power rail clamps the base node at a low potential level when the emitter follower transistor element is relatively non-conducting and establishes the input threshold voltage level. A second clamp circuit coupled to the base node of the emitter follower transistor element clamps the base node at a high potential level for limiting base drive current to the phase splitter transistor element from the emitter follower transistor element. The second clamp circuit limits saturation of the phase splitter transistor element and improves switching speed. The second clamp circuit is preferably coupled between the base node of the emitter follower transistor element and a collector node of the phase splitter transistor element and includes a "programmable" resistor voltage drop component for limiting operation of the phase splitter transistor element to the desired operating region.

公开(公告)号：US5021687A

公开(公告)日：1991-06-04

申请号：US473533

申请日：1990-02-01

申请人： Roy Yarbrough ,  Ernest D. Haacke ,  Lars G. Jansson

发明人： Roy Yarbrough ,  Ernest D. Haacke ,  Lars G. Jansson

IPC分类号： H03K17/66 ,  H03K3/037 ,  H03K3/2893 ,  H03K19/003 ,  H03K19/088

CPC分类号： H03K3/0377 ,  H03K19/00353 ,  H03K3/2893

摘要： A TTL inverter buffer circuit is provided with a switched current that produces hysteresis in the threshold values. The current is switched on by a control circuit when the input logic is low and off when the logic is high. The control circuit receives its sense from the logic state so that when the input logic is low a high threshold is created and when the input logic is high a low threshold is created. The difference is the circuit hysteresis voltage which is dependent upon the switched current and a resistor.

公开(公告)号：US4988898A

公开(公告)日：1991-01-29

申请号：US352169

申请日：1989-05-15

申请人： Lars G. Jansson

发明人： Lars G. Jansson

IPC分类号： G11C11/414 ,  H03K19/013 ,  H03K19/018

CPC分类号： H03K19/01812 ,  H03K19/013 ,  H03K19/01806

摘要： An ECL/CML to TTL translator circuit couples the output of an ECL/CML gate to the input of a TTL gate. The ECL/CML gate operates with reference to a first power rail higher reference voltage level with transistor elements operating in the non-saturation operating region. The TTL gate operates with reference to a second power rail lower reference voltage level with transistor elements operating in the saturation operating region. The translator circuit includes a reference voltage level shifting constant current non-switching current mirror circuit coupled to the output of the ECL/CML gate. The current mirror circuit shifts the reference voltage level of the ECL/CML gate output from the higher reference voltage level to the lower reference voltage level and delivers a reference voltage level shifted output signal. An operating region translating emitter follower output buffer circuit is coupled to receive the voltage level shifted output signal and drive the input of the TTL gate in the saturation region. The circuit functions of reference voltage level shifting and of operating region translating are thereby separately performed by separate components. The TTL gate input is a phase splitter transistor element. A resistor pulldown discharges the phase splitter transistor element. Base drive to the phase splitter transistor element is limited by a base drive limiting anti-saturation clamp. More generally, an overdrive and anti-saturation clamp circuit provides high speed switching of the phase splitter or other TTL switching transistor element.

公开(公告)号：US4958090A

公开(公告)日：1990-09-18

申请号：US320281

申请日：1989-03-06

申请人： Lars G. Jansson

发明人： Lars G. Jansson

IPC分类号： H03K3/286 ,  H03K3/288 ,  H03K19/003 ,  H03K19/088

CPC分类号： H03K3/288 ,  H03K19/00307 ,  H03K19/00353 ,  H03K19/088

摘要： Dual phase splitter transistor elements, an output phase splitter transistor element and a secondary phase splitter transistor element, are coupled in current mirror configuration in a TTL output buffer circuit. The output phase splitter transistor element is coupled to the pullup and pulldown transistor elements for controlling the respective conducting states of the pullup and pulldown transistor elements. The collector of the secondary phase splitter transistor element is coupled in a supplemental circuit which can have a variable load without direct connection to the pullup transistor element and output. A low impedance current sourcing active transistor element is coupled in emitter follower configuration at the collector node of the secondary phase splitter transistor element for supplying mirroring current through the emitter of the secondary phase splitter transistor element to reduce current hogging at the dual phase splitter transistor elements. The current sourcing transistor element is coupled in parallel with the supplemental circuit thereby providing a variable current which varies inversely with the collector current supplied by the supplemental circuit. The invention is applied in a JK flip flop circuit as the output buffer circuits with the collector of the secondary phase splitter transistor element coupled to the cross feedback circuit. The cross feedback transistor element in the cross feedback circuit is therefore isolated from the pullup transistor element and output avoiding feedback transistor breakdown when the output is at high potential. The current sourcing transistor element prevents current hogging between the dual phase splitter transistor elements.