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    Detector for alpha particle or cosmic ray
    1.
    发明授权
    Detector for alpha particle or cosmic ray 失效
    α粒子或宇宙射线探测器

    公开(公告)号：US07057180B2

    公开(公告)日：2006-06-06

    申请号：US10604416

    申请日：2003-07-18

    申请人： John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Stephen V. Kosonocky ,  Randy W. Mann ,  Jeffery H. Oppold ,  Norman J. Rohrer

    发明人： John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Stephen V. Kosonocky ,  Randy W. Mann ,  Jeffery H. Oppold ,  Norman J. Rohrer

    IPC分类号： G01T1/24

    CPC分类号： G11C11/4125

    摘要： A detector circuit and method for detecting a silicon well voltage or current to indicate an alpha particle or cosmic ray strike of the silicon well. One significant application for the detection circuit of the present invention is for the redundancy repair latches that are used in SRAMs. The redundancy repair latches are normally written once at power-up to record failed latch data and are not normally written again. If one of the latches changes states due to an SER (Soft Error Rate-such as a strike by an alpha particle or cosmic ray) event, the repair data in the redundancy latches of the SRAM would now be incorrectly mapped. The detector circuit and method monitors the latches for the occurrence of an SER event, and responsive thereto issues a reload of the repair data to the redundancy repair latches. A first embodiment of the detector circuit differentially detects the floating voltages of first and second silicon wells during periods of non-operation of the circuits fabricated in the first and second silicon wells. In a second embodiment, a detector circuit monitors the background voltage level of a single silicon well over first and second consecutive periods of time. A second application for the detection circuit is for traditional logic circuits.

    摘要翻译： 一种用于检测硅阱电压或电流以指示硅阱的α粒子或宇宙射线冲击的检测器电路和方法。 本发明的检测电路的一个重要应用是用于SRAM中的冗余修复锁存器。 冗余修复锁存器在上电时通常写入一次，以记录失败的锁存数据，并且通常不会再次写入。 如果其中一个锁存器由于SER（软错误率（例如α粒子或宇宙射线的击穿））事件而改变状态，则SRAM的冗余锁存器中的修复数据现在将被错误地映射。 检测器电路和方法监视锁存器以发生SER事件，并且响应于此，将修复数据重新加载到冗余修复锁存器。 检测器电路的第一实施例在第一和第二硅阱中制造的电路的非操作期间差分地检测第一和第二硅阱的浮置电压。 在第二实施例中，检测器电路在第一和第二连续时间段内监测单个硅阱的背景电压电平。 检测电路的第二个应用是传统的逻辑电路。

    Methods and apparatus for employing feedback body control in cross-coupled inverters
    2.
    发明授权
    Methods and apparatus for employing feedback body control in cross-coupled inverters 失效
    在交叉耦合逆变器中采用反馈体控制的方法和装置

    公开(公告)号：US06891419B2

    公开(公告)日：2005-05-10

    申请号：US10604554

    申请日：2003-07-30

    申请人： Paul D. Kartschoke ,  Stephen V. Kosonocky ,  Randy W. Mann ,  Norman J. Rohrer

    发明人： Paul D. Kartschoke ,  Stephen V. Kosonocky ,  Randy W. Mann ,  Norman J. Rohrer

    IPC分类号： H03K3/037 ,  H03K3/356

    CPC分类号： H03K3/356104 ,  H03K3/0375

    摘要： In a first aspect, a cross-coupled inverter is provided that includes a first inverter circuit having a first NFET coupled to a first PFET and a second inverter circuit having a second NFET coupled to a second PFET. The second inverter circuit is cross-coupled with the first inverter circuit at a plurality of nodes. The body of at least one of the first NFET, the second NFET, the first PFET and the second PFET is coupled so as to form a feedback path that reduces discharging at one or more of the plurality of nodes in response to a soft error event at the cross-coupled inverter.

    摘要翻译： 在第一方面，提供一种交叉耦合的反相器，其包括具有耦合到第一PFET的第一NFET的第一反相器电路和具有耦合到第二PFET的第二NFET的第二反相器电路。 第二逆变器电路在多个节点处与第一反相器电路交叉耦合。 第一NFET，第二NFET，第一PFET和第二PFET中的至少一个的主体被耦合以形成反馈路径，其减少响应于软错误事件的多个节点中的一个或多个的放电 在交叉耦合的逆变器。

    Error correcting logic system
    3.
    发明授权
    Error correcting logic system 有权
    错误校正逻辑系统

    公开(公告)号：US07642813B2

    公开(公告)日：2010-01-05

    申请号：US11850857

    申请日：2007-09-06

    申请人： Kerry Bernstein ,  Philip G. Emma ,  John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Norman J. Rohrer

    发明人： Kerry Bernstein ,  Philip G. Emma ,  John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Norman J. Rohrer

    IPC分类号： H03K19/20 ,  H03K19/094 ,  H03K19/003

    CPC分类号： H03K19/007

    摘要： The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors. Also, there is provided a design structure embodied in a machine readable medium used in a design process, and which includes such error correcting logic system.

    摘要翻译： 本发明包括纠错逻辑系统，其允许仅使用一个冗余单元来硬化关键电路并且不损失电路性能。 该系统提供互连门，其抑制馈送到互连门的至少两个冗余动态逻辑门之一的故障。 该系统适用于动态或静态逻辑系统。 该系统防止故障传播，不仅解决软错误，而且还会引起噪声引起的错误。 此外，提供了在设计过程中使用的机器可读介质中体现的设计结构，并且包括这种纠错逻辑系统。

    ERROR CORRECTING LOGIC SYSTEM
    4.
    发明申请
    ERROR CORRECTING LOGIC SYSTEM 有权
    错误修正逻辑系统

    公开(公告)号：US20090002015A1

    公开(公告)日：2009-01-01

    申请号：US11850857

    申请日：2007-09-06

    申请人： Kerry Bernstein ,  Philip G. Emma ,  John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Norman J. Rohrer

    发明人： Kerry Bernstein ,  Philip G. Emma ,  John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Norman J. Rohrer

    IPC分类号： H03K19/003

    CPC分类号： H03K19/007

    摘要： The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors. Also, there is provided a design structure embodied in a machine readable medium used in a design process, and which includes such error correcting logic system.

    摘要翻译： 本发明包括纠错逻辑系统，其允许仅使用一个冗余单元来硬化关键电路并且不损失电路性能。 该系统提供互连门，其抑制馈送到互连门的至少两个冗余动态逻辑门之一的故障。 该系统适用于动态或静态逻辑系统。 该系统防止故障传播，不仅解决软错误，而且还会引起噪声引起的错误。 此外，提供了在设计过程中使用的机器可读介质中体现的设计结构，并且包括这种纠错逻辑系统。

    Error correcting logic system
    5.
    发明授权
    Error correcting logic system 有权
    错误校正逻辑系统

    公开(公告)号：US07471115B2

    公开(公告)日：2008-12-30

    申请号：US11926386

    申请日：2007-10-29

    申请人： Kerry Bernstein ,  Philip G. Emma ,  John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Norman J. Rohrer

    发明人： Kerry Bernstein ,  Philip G. Emma ,  John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Norman J. Rohrer

    IPC分类号： H03K19/096 ,  H03K19/094

    CPC分类号： H03K19/007

    摘要： The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.

    摘要翻译： 本发明包括纠错逻辑系统，其允许仅使用一个冗余单元来硬化关键电路并且不损失电路性能。 该系统提供互连门，其抑制馈送到互连门的至少两个冗余动态逻辑门之一的故障。 该系统适用于动态或静态逻辑系统。 该系统防止故障传播，不仅解决软错误，而且还会引起噪声引起的错误。

    Body-contacted and double gate-contacted differential logic circuit and method of operation
    8.
    发明授权
    Body-contacted and double gate-contacted differential logic circuit and method of operation 有权
    身体接触和双门接触差分逻辑电路及其操作方法

    公开(公告)号：US06580293B1

    公开(公告)日：2003-06-17

    申请号：US09683325

    申请日：2001-12-14

    申请人： Kerry Bernstein ,  Peter E. Cottrell ,  Stephen V. Kosonocky ,  David Meltzer ,  Edward J. Nowak ,  Kevin J. Nowka ,  Norman J. Rohrer

    发明人： Kerry Bernstein ,  Peter E. Cottrell ,  Stephen V. Kosonocky ,  David Meltzer ,  Edward J. Nowak ,  Kevin J. Nowka ,  Norman J. Rohrer

    IPC分类号： H03K19096

    CPC分类号： H03K19/1737 ,  H03K3/356113 ,  H03K19/0963

    摘要： A differential logic circuit (20, 120, 220, 320, 420 and 520) designed to ensure stability of the output of the circuit. The logic circuit includes a differential load structure (22, 122, 222, 322, 422) that is connected to evaluate transistors (50, 52, 54, 56). In several embodiments, the outputs of the load transistors (30, 32) in the differential load structure are connected to the bodies of the evaluate transistors. In the other embodiments, the outputs of the load transistors in the differential structure are connected to one of the gates of a double-gated evaluate transistors. Level-shifting output buffers (160, 178) are used in connection with the embodiments of the invention that do not include double-gated evaluate transistors.

    摘要翻译： 设计用于确保电路输出的稳定性的差分逻辑电路（20,120,220,320,420和520）。 逻辑电路包括被连接以评估晶体管（50,52,54,56）的差分负载结构（22,122,222,322,422）。 在几个实施例中，差分负载结构中的负载晶体管（30,32）的输出连接到评估晶体管的主体。 在其他实施例中，差分结构中的负载晶体管的输出连接到双门控评估晶体管的栅极之一。 结合本发明的不包括双门控评估晶体管的实施例，使用电平移位输出缓冲器（160,178）。

    Low power pre-discharged ratio logic
    9.
    发明授权
    Low power pre-discharged ratio logic 失效
    低功率预放电比逻辑

    公开(公告)号：US5572150A

    公开(公告)日：1996-11-05

    申请号：US419630

    申请日：1995-04-10

    申请人： Paul D. Kartschoke ,  Norman J. Rohrer

    发明人： Paul D. Kartschoke ,  Norman J. Rohrer

    IPC分类号： H03K19/20 ,  H03K3/356 ,  H03K19/00 ,  H03K19/096

    CPC分类号： H03K19/0013 ,  H03K3/356113

    摘要： A circuit and method are provided for reducing the DC power consumption of clocked ratioed digital logic circuits. The circuit includes switching circuitry designed to analyze the voltage transitions of a ratioed digital logic circuit and based on such transitions, control the DC current flow through the entire circuit. Through the regulation of DC current flow through a digital logic circuit, the present invention reduces the detrimental effects of hot-electron effects and electromigration concerns which cause digital circuitry to fail. The circuit and method are illustrated by way of a ratioed logic NOR function employing MOSFET technology.

    摘要翻译： 提供了一种电路和方法，用于降低计时比数字逻辑电路的直流功耗。 电路包括设计用于分析比例数字逻辑电路的电压转换并基于这种转变的开关电路，控制通过整个电路的直流电流。 通过调节通过数字逻辑电路的直流电流，本发明减少了导致数字电路故障的热电子效应和电迁移问题的有害影响。 电路和方法通过采用MOSFET技术的比例逻辑NOR功能来说明。

    Methodology for fixing Qcrit at design timing impact
    10.
    发明授权
    Methodology for fixing Qcrit at design timing impact 失效
    在设计时间上影响Qcrit的方法

    公开(公告)号：US06954916B2

    公开(公告)日：2005-10-11

    申请号：US10604179

    申请日：2003-06-30

    申请人： Kerry Bernstein ,  Philip G. Emma ,  Leendert M. Huisman ,  Paul D. Kartschoke ,  Norman J. Rohrer

    发明人： Kerry Bernstein ,  Philip G. Emma ,  Leendert M. Huisman ,  Paul D. Kartschoke ,  Norman J. Rohrer

    IPC分类号： G06F9/45 ,  G06F17/50

    CPC分类号： G06F17/5022

    摘要： A method and system for simulating an integrated circuit. The method includes the steps of performing a timing analysis of the circuits to ensure that they meet specified timing criteria, performing soft error analysis of the circuits to determine whether they meet specified soft error criteria, and improving those circuits that fail the soft error analysis to improve their resistance to soft errors and having no degradation on timing. Preferably, the improving step includes the step of improving those circuits that fail the soft error analysis by either having an additional voltage source or altering the capacitance of the circuits.

    摘要翻译： 一种用于模拟集成电路的方法和系统。 该方法包括以下步骤：执行电路的定时分析，以确保它们满足规定的时序准则，执行电路的软错误分析，以确定它们是否符合指定的软错误标准，以及改进那些无法通过软错误分析的电路 提高其对软错误的抵抗力，并且在时序上没有劣化。 优选地，改进步骤包括通过具有附加电压源或改变电路的电容来改进不能通过软误差分析的那些电路的步骤。