公开(公告)号：US06580293B1

公开(公告)日：2003-06-17

申请号：US09683325

申请日：2001-12-14

申请人： Kerry Bernstein ,  Peter E. Cottrell ,  Stephen V. Kosonocky ,  David Meltzer ,  Edward J. Nowak ,  Kevin J. Nowka ,  Norman J. Rohrer

发明人： Kerry Bernstein ,  Peter E. Cottrell ,  Stephen V. Kosonocky ,  David Meltzer ,  Edward J. Nowak ,  Kevin J. Nowka ,  Norman J. Rohrer

IPC分类号： H03K19096

CPC分类号： H03K19/1737 ,  H03K3/356113 ,  H03K19/0963

摘要： A differential logic circuit (20, 120, 220, 320, 420 and 520) designed to ensure stability of the output of the circuit. The logic circuit includes a differential load structure (22, 122, 222, 322, 422) that is connected to evaluate transistors (50, 52, 54, 56). In several embodiments, the outputs of the load transistors (30, 32) in the differential load structure are connected to the bodies of the evaluate transistors. In the other embodiments, the outputs of the load transistors in the differential structure are connected to one of the gates of a double-gated evaluate transistors. Level-shifting output buffers (160, 178) are used in connection with the embodiments of the invention that do not include double-gated evaluate transistors.

摘要翻译： 设计用于确保电路输出的稳定性的差分逻辑电路（20,120,220,320,420和520）。 逻辑电路包括被连接以评估晶体管（50,52,54,56）的差分负载结构（22,122,222,322,422）。 在几个实施例中，差分负载结构中的负载晶体管（30,32）的输出连接到评估晶体管的主体。 在其他实施例中，差分结构中的负载晶体管的输出连接到双门控评估晶体管的栅极之一。 结合本发明的不包括双门控评估晶体管的实施例，使用电平移位输出缓冲器（160,178）。

公开(公告)号：US08285765B2

公开(公告)日：2012-10-09

申请号：US11608907

申请日：2006-12-11

申请人： Lei Chen ,  Hung C. Ngo ,  Kevin J. Nowka

发明人： Lei Chen ,  Hung C. Ngo ,  Kevin J. Nowka

IPC分类号： G06F7/38

CPC分类号： G06F9/3885 ,  G06F7/575 ,  G06F9/30021 ,  G06F9/30094 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3844 ,  G06F9/3857

摘要： A system and method for implementing arithmetic logic unit (ALU) support for value-based control dependence sequences. According to a first embodiment of the present invention, an ALU generates a carry-out signal designating one of a first and second value as a larger value. In response to the carry-out signal, the ALU updates a storage location with a third value, which is the larger value. According to a second embodiment of the present invention, an ALU generates a carry-out signal designating one of a first and second value as a larger value. In response to the carry-out signal, the ALU updates a storage location with a third value. The third value is a fourth value, if the carry-out signal designates the first value as the larger value or the third value is a fifth value, if the carry-out signal designates the second value as the larger value.

摘要翻译： 用于实现算术逻辑单元（ALU）的系统和方法支持基于值的控制依赖序列。 根据本发明的第一实施例，ALU产生指定第一和第二值中的一个作为较大值的进位输出信号。 响应于进位信号，ALU用第三个值更新存储位置，该值是较大的值。 根据本发明的第二实施例，ALU产生指定第一和第二值中的一个作为较大值的进位信号。 响应于进位信号，ALU用第三个值更新存储位置。 如果进位信号指定第二值作为较大值，则第三值是第四值，如果进位信号指定第一值作为较大值或第三值是第五值。

公开(公告)号：US07864625B2

公开(公告)日：2011-01-04

申请号：US12244286

申请日：2008-10-02

申请人： Gary D. Carpenter ,  Jente B. Kuang ,  Kevin J. Nowka ,  Liang-Teck Pang

发明人： Gary D. Carpenter ,  Jente B. Kuang ,  Kevin J. Nowka ,  Liang-Teck Pang

IPC分类号： G11C8/18 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C11/417 ,  G11C7/22 ,  G11C11/419

摘要： A delay circuit has a fixed delay path at a lower voltage level, a level converter, and an adjustable delay path at a higher voltage level. The fixed delay path includes an inverter chain, and the adjustable delay path includes serially-connected delay elements selectively connected to the circuit output. In an application for a local clock buffer of a static, random-access memory (SRAM), the lower voltage level is that of the local clock buffer, and the higher voltage level is that of the SRAM. These voltages may vary in response to dynamic voltage scaling, requiring re-calibration of the adjustable delay path. The adjustable delay path may be calibrated by progressively increasing the read access time of the SRAM array until a contemporaneous read operation returns the correct output, or by using a replica SRAM path to simulate variations in delay with changes in voltage supply.

摘要翻译： 延迟电路具有在较低电压电平的固定延迟路径，电平转换器和在较高电压电平下的可调延迟路径。 固定延迟路径包括反相器链，并且可调延迟路径包括选择性地连接到电路输出的串联连接的延迟元件。 在静态随机存取存储器（SRAM）的本地时钟缓冲器的应用中，较低的电压电平是本地时钟缓冲器的电平，而较高的电压电平是SRAM的电压电平。 这些电压可以响应于动态电压缩放而变化，需要重新校准可调延迟路径。 可调整的延迟路径可以通过逐渐增加SRAM阵列的读取访问时间来校准，直到同时读取操作返回正确的输出，或者通过使用复制SRAM路径来模拟延迟随电压变化的变化。

公开(公告)号：US20100085823A1

公开(公告)日：2010-04-08

申请号：US12244286

申请日：2008-10-02

申请人： Gary D. Carpenter ,  Jente B. Kuang ,  Kevin J. Nowka ,  Liang-Teck Pang

发明人： Gary D. Carpenter ,  Jente B. Kuang ,  Kevin J. Nowka ,  Liang-Teck Pang

IPC分类号： G11C7/00 ,  G11C8/18 ,  H03H11/26 ,  H03K3/00 ,  H03L5/00 ,  G11C8/08

CPC分类号： G11C11/417 ,  G11C7/22 ,  G11C11/419

摘要： A delay circuit has a fixed delay path at a lower voltage level, a level converter, and an adjustable delay path at a higher voltage level. The fixed delay path includes an inverter chain, and the adjustable delay path includes serially-connected delay elements selectively connected to the circuit output. In an application for a local clock buffer of a static, random-access memory (SRAM), the lower voltage level is that of the local clock buffer, and the higher voltage level is that of the SRAM. These voltages may vary in response to dynamic voltage scaling, requiring re-calibration of the adjustable delay path. The adjustable delay path may be calibrated by progressively increasing the read access time of the SRAM array until a contemporaneous read operation returns the correct output, or by using a replica SRAM path to simulate variations in delay with changes in voltage supply.

摘要翻译： 延迟电路具有在较低电压电平的固定延迟路径，电平转换器和在较高电压电平下的可调延迟路径。 固定延迟路径包括反相器链，并且可调延迟路径包括选择性地连接到电路输出的串联连接的延迟元件。 在静态随机存取存储器（SRAM）的本地时钟缓冲器的应用中，较低的电压电平是本地时钟缓冲器的电平，而较高的电压电平是SRAM的电压电平。 这些电压可以响应于动态电压缩放而变化，需要重新校准可调延迟路径。 可调整的延迟路径可以通过逐渐增加SRAM阵列的读取访问时间来校准，直到同时读取操作返回正确的输出，或者通过使用复制SRAM路径来模拟延迟随电压变化的变化。

公开(公告)号：US07668037B2

公开(公告)日：2010-02-23

申请号：US11935566

申请日：2007-11-06

申请人： Gary D. Carpenter ,  Fadi H. Gebara ,  Jerry C. Kao ,  Jente B Kuang ,  Kevin J. Nowka ,  Liang-Teck Pang

发明人： Gary D. Carpenter ,  Fadi H. Gebara ,  Jerry C. Kao ,  Jente B Kuang ,  Kevin J. Nowka ,  Liang-Teck Pang

IPC分类号： G11C8/00

CPC分类号： G11C7/22 ,  G11C7/12 ,  G11C7/222 ,  G11C29/02 ,  G11C29/023 ,  G11C29/14 ,  G11C29/50 ,  G11C29/50012

摘要： A storage array including a local clock buffer with programmable timing provides a mechanism for evaluating circuit timing internal to the storage array. The local clock buffer can independently adjust the pulse width of a local clock that controls the wordline and local bitline precharge pulses and the pulse width of a delayed clock that controls the global bitline precharge, evaluate and read data latching. The delay between the local clock and the delayed clock can also be adjusted. By varying the pulse widths of the local and delayed clock signal, along with the inter-clock delay, the timing margins of each cell in the array can be evaluated by reading and writing the cell with varying pulse width and clock delay. The resulting evaluation can be used to evaluate timing margin variation within a die, as well variation from die-to-die and under varying environments, e.g., voltage and temperature variation.

摘要翻译： 包括具有可编程时序的本地时钟缓冲器的存储阵列提供了用于评估存储阵列内部的电路定时的机制。 本地时钟缓冲器可以独立调节控制字线和本地位线预充电脉冲的本地时钟的脉冲宽度以及控制全局位线预充电，评估和读取数据锁存的延迟时钟的脉冲宽度。 本地时钟和延迟时钟之间的延迟也可以调整。 通过改变本地和延迟的时钟信号的脉冲宽度以及时钟间延迟，可以通过读取和写入具有变化的脉冲宽度和时钟延迟的单元来评估阵列中每个单元的定时裕度。 所得到的评估可用于评估管芯内的时间裕度变化，以及在管芯到管芯之间以及在变化的环境（例如电压和温度变化）下的变化。

公开(公告)号：US07564259B2

公开(公告)日：2009-07-21

申请号：US11301728

申请日：2005-12-13

申请人： Kanak B. Agarwal ,  Damir A. Jamsek ,  Kevin J. Nowka

发明人： Kanak B. Agarwal ,  Damir A. Jamsek ,  Kevin J. Nowka

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/0016

摘要： A digital circuit with dynamic power and performance control via per-block selectable operating voltage level permits dynamic tailoring of operating power to processing demand and/or compensation for process variation. A set of processing blocks having a power supply selectable from two different power supply voltage levels is provided. The power level of the overall circuit is set by selecting the power supply voltage for each block to yield a combination of blocks that meets operating requirements. Alternatively, one circuit per pair from a set of pairs of redundant logic blocks supplied by the different power supply voltage levels can be selected to meet the operating requirements. The unselected blocks can be disabled by disabling foot devices or disabling transitions at the inputs to the unselected blocks. Performance measurement and feedback circuits can be included to tune the power consumption and performance level of the circuit to meet an expected level.

摘要翻译： 具有通过每块可选工作电压电平的动态功率和性能控制的数字电路允许动态定制工作电源以处理需求和/或对工艺变化的补偿。 提供了具有可从两个不同电源电压电平选择的电源的一组处理块。 通过选择每个块的电源电压来设置整个电路的功率电平，以产生满足运行要求的块组合。 或者，可以选择由不同电源电压电平提供的一组冗余逻辑块中的每对一个电路以满足操作要求。 可以通过禁用脚装置或禁用未选择块的输入上的转换来禁用未选择的块。 可以包括性能测量和反馈电路来调整电路的功耗和性能水平以达到预期的水平。

公开(公告)号：US07545690B2

公开(公告)日：2009-06-09

申请号：US11741187

申请日：2007-04-27

申请人： Jente B. Kuang ,  Jerry C. Kao ,  Hung Cai Ngo ,  Kevin J. Nowka

发明人： Jente B. Kuang ,  Jerry C. Kao ,  Hung Cai Ngo ,  Kevin J. Nowka

IPC分类号： G11C7/00 ,  G11C11/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/50012 ,  G11C2029/1204

摘要： A method for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in complement fashion to form a cascade of memory cells. The drive devices can be inverters and the inverters can be sized to simulate the bitline read pre-charge device and the write state-forcing device so that the cascade operates under the same loading/drive conditions as the operational with memory cell read/write circuits. The last and first bitline in the row can be cascaded, providing a ring oscillator or the delay of the cascade can be measured in response to a transition introduced at the head of the cascade. Weak read and/or weak write conditions can be measured by selective loading.

摘要翻译： 用于评估存储器单元性能的方法在实际存储器电路环境中提供电路延迟和性能测量。 存储器阵列中的行与一组驱动装置一起被启用，这些驱动装置将每个位线对以互补方式耦合到下一个位置以形成级联的存储器单元。 驱动装置可以是逆变器，并且逆变器的大小可以模拟位线读取预充电装置和写入状态强制装置，使得级联在与存储单元读/写电路的操作相同的加载/驱动条件下操作 。 该行中的最后一个和第一个位线可以级联，提供环形振荡器，或者响应于在级联头部引入的转换，可以测量级联的延迟。 弱写入条件和/或弱写入条件可以通过选择性加载来测量。

公开(公告)号：US20090116312A1

公开(公告)日：2009-05-07

申请号：US11935566

申请日：2007-11-06

申请人： Gary D. Carpenter ,  Fadi H. Gebara ,  Jerry C. Kao ,  Jente B. Kuang ,  Kevin J. Nowka ,  Liang-Teck Pang

发明人： Gary D. Carpenter ,  Fadi H. Gebara ,  Jerry C. Kao ,  Jente B. Kuang ,  Kevin J. Nowka ,  Liang-Teck Pang

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C7/22 ,  G11C7/12 ,  G11C7/222 ,  G11C29/02 ,  G11C29/023 ,  G11C29/14 ,  G11C29/50 ,  G11C29/50012

摘要： A storage array including a local clock buffer with programmable timing provides a mechanism for evaluating circuit timing internal to the storage array. The local clock buffer can independently adjust the pulse width of a local clock that controls the wordline and local bitline precharge pulses and the pulse width of a delayed clock that controls the global bitline precharge, evaulate and read data latching. The delay between the local clock and the delayed clock can also be adjusted. By varying the pulse widths of the local and delayed clock signal, along with the inter-clock delay, the timing margins of each cell in the array can be evaluated by reading and writing the cell with varying pulse width and clock delay. The resulting evaluation can be used to evaluate timing margin variation within a die, as well variation from die-to-die and under varying environments, e.g., voltage and temperature variation.

摘要翻译： 包括具有可编程时序的本地时钟缓冲器的存储阵列提供了用于评估存储阵列内部的电路定时的机制。 本地时钟缓冲器可以独立调节控制字线和本地位线预充电脉冲的本地时钟的脉冲宽度以及控制全局位线预充电，延迟和读取数据锁存的延迟时钟的脉冲宽度。 本地时钟和延迟时钟之间的延迟也可以调整。 通过改变本地和延迟的时钟信号的脉冲宽度以及时钟间延迟，可以通过读取和写入具有变化的脉冲宽度和时钟延迟的单元来评估阵列中每个单元的定时裕度。 所得到的评估可用于评估管芯内的时间裕度变化，以及在管芯到管芯之间以及在变化的环境（例如电压和温度变化）下的变化。

公开(公告)号：US07129754B2

公开(公告)日：2006-10-31

申请号：US11082805

申请日：2005-03-17

申请人： Hung C. Ngo ,  Jayakumaran Sivagnaname ,  Kevin J. Nowka ,  Robert K. Montoye

发明人： Hung C. Ngo ,  Jayakumaran Sivagnaname ,  Kevin J. Nowka ,  Robert K. Montoye

IPC分类号： H03K19/096

CPC分类号： H03K19/0963

摘要： An LSDL circuit replaces the normal clock control of the pre-charge device for the dynamic node with a control signal that is logic zero whenever the circuit is in an active mode and is a logic one when the circuit is in standby mode. The pre-charge device holds the dynamic node at a pre-charged logic one state independent of the clock. During the logic one evaluate time of the clock, the logic tree determines the asserted state of the dynamic node. During the evaluate time, the asserted state is latched by the static LSDL section. The dynamic node then re-charges to the pre-charge state. Since the pre-charge device is not de-gated during the evaluate time, the dynamic node cannot be inadvertently discharged by noise causing an error. Likewise, since the clock does not couple to the pre-charge device a load is removed from the clock tree lowering clock power.

摘要翻译： 只要电路处于活动模式，LSDL电路用动态节点的预充电装置的正常时钟控制替代逻辑零的控制信号，并且当电路处于待机模式时，逻辑为逻辑1。 预充电装置将动态节点保持在与时钟无关的预充电逻辑1状态。 在逻辑1期间评估时钟的时间，逻辑树确定动态节点的被断言状态。 在评估时间期间，断言状态由静态LSDL部分锁存。 然后动态节点重新充电到预充电状态。 由于在评估时间期间预充电装置没有被去门，所以动态节点不能被无意中的噪声放电，导致错误。 类似地，由于时钟不耦合到预充电装置，所以从时钟树中降低时钟功率的负载被去除。

公开(公告)号：US06975134B2

公开(公告)日：2005-12-13

申请号：US10821048

申请日：2004-04-08

申请人： Jente B. Kuang ,  Hung C. Ngo ,  Kevin J. Nowka

发明人： Jente B. Kuang ,  Hung C. Ngo ,  Kevin J. Nowka

IPC分类号： H03K17/16 ,  H03K19/00 ,  H03K19/003 ,  H03K19/017

CPC分类号： H03K19/00361 ,  H03K19/0016 ,  H03K19/01721

摘要： A buffer/driver having large output devices for driving multiple loads is configured with three parallel paths. The first logic path is made of small devices and is configured to provide the logic function of the buffer/driver without the ability to drive large loads. Second and third logic paths have the logic function of the first logic path up to the last inverting stage. The last inverting stage in each path is a single device for driving the logic states of the buffer output. The second and third logic paths have power-gating that allows the input to the pull-up and pull-down devices to float removing gate-leakage voltage stress. When the second and third logic paths are power-gated, the first logic path provides a keeper function to hold the logic state of the buffer output. The buffer/driver may be an inverter, non-inverter, or provide a multiple input logic function.

摘要翻译： 具有用于驱动多个负载的大输出装置的缓冲器/驱动器配置有三个并行路径。 第一个逻辑路径由小型设备组成，并配置为提供缓冲器/驱动器的逻辑功能，而无需驱动大负载。 第二和第三逻辑路径具有直到上一个反相级的第一逻辑路径的逻辑功能。 每个路径中的最后一个反相级是用于驱动缓冲区输出逻辑状态的单个器件。 第二和第三逻辑路径具有电源门控，允许上拉和下拉器件的输入漂移去除栅极泄漏电压应力。 当第二和第三逻辑路径是电源门控时，第一逻辑路径提供保持器功能以保持缓冲器输出的逻辑状态。 缓冲器/驱动器可以是逆变器，非逆变器，或提供多输入逻辑功能。