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    Method and apparatus for detecting the endpoint of a chemical-mechanical polishing operation using optical techniques
    1.
    发明授权
    Method and apparatus for detecting the endpoint of a chemical-mechanical polishing operation using optical techniques 有权
    使用光学技术检测化学机械抛光操作的终点的方法和装置

    公开(公告)号：US06809032B1

    公开(公告)日：2004-10-26

    申请号：US10136513

    申请日：2002-05-01

    申请人： Frank Mauersberger ,  Peter J. Beckage ,  Paul R. Besser ,  Frederick N. Hause ,  Errol Todd Ryan ,  William S. Brennan ,  John A. Iacoponi

    发明人： Frank Mauersberger ,  Peter J. Beckage ,  Paul R. Besser ,  Frederick N. Hause ,  Errol Todd Ryan ,  William S. Brennan ,  John A. Iacoponi

    IPC分类号： H01L21302

    CPC分类号： B24B37/013 ,  B24B49/12 ,  H01L21/3212 ,  H01L21/76801 ,  H01L21/7684 ,  H01L21/76877

    摘要： In another aspect of the present invention, a system for detecting an endpoint in a polishing process is provided. The system comprises a polishing tool, a controllable light source, a sensor, and a controller. The polishing tool is capable of polishing a surface of a semiconductor device, wherein the semiconductor device includes a first layer comprised of a first material and a second layer comprised of a second material. The first layer is positioned above the second layer. The controllable light source is capable of delivering light having one of a plurality of a preselected frequencies to the surface of the semiconductor device. The sensor is capable of detecting the light reflected from the surface of the semiconductor device. The controller is capable of determining the second material, instructing the controllable light source to deliver light of one of the frequencies in response to the second material, comparing the reflected light to a preselected setpoint, and modifying the polishing process in response to the reflected light exceeding the preselected setpoint.

    摘要翻译： 在本发明的另一方面，提供了一种用于在抛光过程中检测端点的系统。 该系统包括抛光工具，可控光源，传感器和控制器。 抛光工具能够抛光半导体器件的表面，其中半导体器件包括由第一材料构成的第一层和由第二材料构成的第二层。 第一层位于第二层之上。 可控光源能够将具有多个预选频率中的一个的光传送到半导体器件的表面。 传感器能够检测从半导体器件的表面反射的光。 所述控制器能够确定所述第二材料，指示所述可控光源响应于所述第二材料传送所述频率之一的光，将所述反射光与预选设定值进行比较，以及响应于所述反射光修改所述抛光过程 超过预选设定值。

    Contact each methodology and integration scheme
    2.
    发明授权
    Contact each methodology and integration scheme 有权
    接触蚀刻方法和集成方案

    公开(公告)号：US06413846B1

    公开(公告)日：2002-07-02

    申请号：US09712501

    申请日：2000-11-14

    申请人： Paul R. Besser ,  Errol Todd Ryan ,  Frederick N. Hause ,  Frank Mauersberger ,  William S. Brennan ,  John A. Iacoponi ,  Peter J. Beckage

    发明人： Paul R. Besser ,  Errol Todd Ryan ,  Frederick N. Hause ,  Frank Mauersberger ,  William S. Brennan ,  John A. Iacoponi ,  Peter J. Beckage

    IPC分类号： H01L2144

    CPC分类号： H01L21/76897 ,  H01L21/76802 ,  Y10S438/97

    摘要： A method of forming conductive contacts or an integrated circuit device is disclosed herein. In one embodiment, the method comprises forming a transistor above a semiconducting substrate, and forming a first layer comprised of an orthosilicate glass material above the transistor and the substrate. The method further comprises forming a second layer comprised of an insulating material above the first layer, and performing at least one etching process to define an opening in the second layer for a conductive contact to be formed therein, wherein the first layer comprised of an orthosilicate glass material acts as an etch stop layer during the etching of the opening in the second layer.

    摘要翻译： 本文公开了一种形成导电触头或集成电路器件的方法。 在一个实施例中，该方法包括在半导体衬底上形成晶体管，以及在晶体管和衬底之上形成由原硅酸盐玻璃材料组成的第一层。 该方法还包括在第一层之上形成由绝缘材料构成的第二层，并且执行至少一个蚀刻工艺以在第二层中限定用于要在其中形成的导电接触的开口，其中，由原硅酸盐 玻璃材料在蚀刻第二层中的开口期间用作蚀刻停止层。

    Test structure for providing depth of polish feedback
    3.
    发明授权
    Test structure for providing depth of polish feedback 失效
    提供抛光反馈深度的测试结构

    公开(公告)号：US06514858B1

    公开(公告)日：2003-02-04

    申请号：US09829202

    申请日：2001-04-09

    申请人： Frederick N. Hause ,  Paul R. Besser ,  Frank Mauersberger ,  Errol Todd Ryan ,  William S. Brennan ,  John A. Iacoponi ,  Peter J. Beckage

    发明人： Frederick N. Hause ,  Paul R. Besser ,  Frank Mauersberger ,  Errol Todd Ryan ,  William S. Brennan ,  John A. Iacoponi ,  Peter J. Beckage

    IPC分类号： H01L214763

    CPC分类号： H01L22/34 ,  B24B37/042 ,  B24B49/00 ,  H01L21/31053 ,  H01L21/7684 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A test structure useful in controlling a polishing process of a semiconductor device is provided. The test structure is comprised of a structure layer, a first process layer, and interconnects. The first process layer is positioned above the structure layer and has a plurality of openings formed therein and extending at least partially therethrough to a preselected depth. At least a portion of the plurality of openings have a tapered region progressively narrowing in a direction from the first process layer toward the structure layer. The openings are spaced a preselected distance X apart. The interconnects are formed in the plurality of openings including the tapered region. Thus, as the process layer and interconnects are removed by the polishing process, the distance X increases, indicating the depth of the polishing process.

    摘要翻译： 提供了一种用于控制半导体器件的抛光工艺的测试结构。 测试结构由结构层，第一处理层和互连构成。 第一处理层位于结构层上方，并且具有形成在其中并且至少部分地穿过其延伸到预选深度的多个开口。 多个开口的至少一部分具有在从第一处理层朝向结构层的方向上逐渐变窄的锥形区域。 开口间隔开预定距离X. 互连形成在包括锥形区域的多个开口中。 因此，当通过抛光工艺去除工艺层和互连件时，距离X增加，表示抛光过程的深度。

    Low stress sidewall spacer in integrated circuit technology
    6.
    发明授权
    Low stress sidewall spacer in integrated circuit technology 有权
    集成电路技术中的低应力侧壁间隔

    公开(公告)号：US07005357B2

    公开(公告)日：2006-02-28

    申请号：US10756023

    申请日：2004-01-12

    申请人： Minh Van Ngo ,  Simon Siu-Sing Chan ,  Paul R. Besser ,  Paul L. King ,  Errol Todd Ryan ,  Robert J. Chiu

    发明人： Minh Van Ngo ,  Simon Siu-Sing Chan ,  Paul R. Besser ,  Paul L. King ,  Errol Todd Ryan ,  Robert J. Chiu

    IPC分类号： H01L21/336 ,  H01L21/441

    CPC分类号： H01L29/6659 ,  H01L29/665

    摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate using a low power plasma enhanced chemical vapor deposition process A silicide is formed on the source/drain junctions and on the gate, and an interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.

    摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 使用低功率等离子体增强化学气相沉积工艺在栅极周围形成侧壁间隔物。在源极/漏极结和栅极上形成硅化物，并且在半导体衬底上沉积层间电介质。 然后在层间电介质中形成与硅化物的接触。

    Contact liner in integrated circuit technology
    10.
    发明授权
    Contact liner in integrated circuit technology 有权
    接触式衬板集成电路技术

    公开(公告)号：US07670915B1

    公开(公告)日：2010-03-02

    申请号：US10791096

    申请日：2004-03-01

    申请人： Errol Todd Ryan ,  Paul R. Besser ,  Simon Siu-Sing Chan ,  Robert J. Chiu ,  Mehrdad Mahanpour ,  Minh Van Ngo

    发明人： Errol Todd Ryan ,  Paul R. Besser ,  Simon Siu-Sing Chan ,  Robert J. Chiu ,  Mehrdad Mahanpour ,  Minh Van Ngo

    IPC分类号： H01L21/20

    CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/7833

    摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain junctions and on the gate. An interlayer dielectric having contact holes therein is formed above the semiconductor substrate. Contact liners are formed in the contact holes, and contacts are then formed over the contact liners. The contact liners are nitrides of the contact material, and formed at a temperature below the thermal budget for the silicide.

    摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 在源极/漏极结和栅极上形成硅化物。 在半导体衬底的上方形成有具有接触孔的层间电介质。 接触衬垫形成在接触孔中，然后在接触衬垫上形成接触。 接触衬垫是接触材料的氮化物，并且在低于硅化物的热预算的温度下形成。