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    Modified InAs hall elements
    1.
    发明授权
    Modified InAs hall elements 失效
    修改的InAs大厅元素

    公开(公告)号：US06316124B1

    公开(公告)日：2001-11-13

    申请号：US09482053

    申请日：2000-01-13

    申请人： John Bradley Boos ,  Walter Kruppa ,  Brian R. Bennett ,  Ming-Jey Yang

    发明人： John Bradley Boos ,  Walter Kruppa ,  Brian R. Bennett ,  Ming-Jey Yang

    IPC分类号： B32B1500

    CPC分类号： B32B15/01 ,  Y10T428/12528 ,  Y10T428/12681 ,  Y10T428/12736 ,  Y10T428/2495

    摘要： This invention pertains to more sensitive and more stable electronic devices which can sense electrical and magnetic fields. The devices are characterized by InAs channels confined on both sides thereof by a wide band gap AlSb material; protective layers above the AlSb material; modulation doping above the AlSb material; and layers of the InAs channel material containing 1 to 99 mol percent antimony, with the channel material being deposited in the form of alternating monolayers of InSb and InAs, of a ternary mixture of InAsSb.

    摘要翻译： 本发明涉及可感测电场和磁场的更敏感和更稳定的电子装置。 这些器件的特征在于通过宽带隙AlSb材料限制在其两侧的InAs通道; AlSb材料上方的保护层; AlSb材料上的调制掺杂; 和含有1至99mol％锑的InAs通道材料的层，其中通道材料以InAsb的三元混合物的InSb和InAs的交替单层形式沉积。

    Channel design to reduce impact ionization in heterostructure field-effect transistors
    2.
    发明授权
    Channel design to reduce impact ionization in heterostructure field-effect transistors 失效
    通道设计，以减少异质结场场效应晶体管的影响电离

    公开(公告)号：US6133593A

    公开(公告)日：2000-10-17

    申请号：US358649

    申请日：1999-07-23

    申请人： J. Brad Boos ,  Ming-Jey Yang ,  Brian R. Bennett ,  Doewon Park ,  Walter Kruppa

    发明人： J. Brad Boos ,  Ming-Jey Yang ,  Brian R. Bennett ,  Doewon Park ,  Walter Kruppa

    IPC分类号： H01L29/10 ,  H01L29/20 ,  H01L29/778

    CPC分类号： H01L29/1029 ,  H01L29/7783 ,  H01L29/2003

    摘要： Heterostructure field-effect transistors (HFETs) and other electronic devs are fabricated from a series of semiconductor layers to have reduced impact ionization. On to a first barrier layer there is added a unique second subchannel layer having high quality transport properties for reducing impact ionization. A third barrier layer having a controlled thickness to permit electrons to tunnel through the layer to the subchannel layer is added as a spacer for the fourth main channel layer. A fifth multilayer composite barrier layer is added which has at least a barrier layer in contact with the fourth channel layer and on top a sixth cap layer is applied. The device is completed by adding two ohmic contacts in a spaced apart relationship on the sixth cap layer with a Schottky gate between them which is formed in contact with the fifth barrier layer. The second subchannel layer and the fourth main channel layers are made of materials which have the proper respective energy gaps and ground state energies such that during use the transfer of hot electrons from the main channel into the subchannel is made probable to reduce impact ionization in the main channel. In the preferred AlSb/InAs-based HFETs, the use of an Is InAs subchannel layer under the main InAs channel improves the performance of the HEMTs particularly for gate lengths in the deep-submicron regime. The devices exhibit higher transconductance, lower output conductance, reduced gate leakage current, higher operating drain voltage, and improved frequency performance.

    摘要翻译： 异质结构场效应晶体管（HFET）和其他电子器件由一系列半导体层制造以具有减小的冲击电离。 在第一阻挡层上添加了具有高质量传输性质的独特的第二子通道层，用于减少冲击电离。 作为第四主沟道层的间隔物，添加具有受控厚度以允许电子穿过层到子沟道层的第三阻挡层。 添加了第五多层复合阻挡层，其至少具有与第四沟道层接触的阻挡层，并且在第六层上施加第六层。 通过在第六盖层上以间隔开的关系添加两个欧姆接触，在它们之间形成与第五阻挡层接触形成的肖特基门来完成该器件。 第二子沟道层和第四主沟道层由具有适当的相应能隙和基态能量的材料制成，使得在使用期间，热电子从主通道转移到子通道中是有可能减少在 主渠道 在优选的基于AlSb / InAs的HFET中，主InAs通道下的In InAs子通道层的使用改善了HEMT的性能，特别是对于深亚微米体系中的栅极长度。 器件表现出更高的跨导，更低的输出电导，降低的栅极漏电流，更高的工作漏极电压和改进的频率性能。

    Electronic devices with InAlAsSb/AlSb barrier
    3.
    发明授权
    Electronic devices with InAlAsSb/AlSb barrier 失效
    具有InAlAsSb / AlSb屏障的电子设备

    公开(公告)号：US5798540A

    公开(公告)日：1998-08-25

    申请号：US848203

    申请日：1997-04-29

    申请人： John Bradley Boos ,  Walter Kruppa ,  Doewon Park ,  Brian R. Bennett

    发明人： John Bradley Boos ,  Walter Kruppa ,  Doewon Park ,  Brian R. Bennett

    IPC分类号： H01L21/308 ,  H01L21/338 ,  H01L29/201 ,  H01L29/205 ,  H01L29/778 ,  H01L29/812 ,  H01L29/00

    CPC分类号： H01L29/205 ,  H01L29/201 ,  H01L29/7783

    摘要： An electronic device characterized by a GaAs substrate and a base disposed n the substrate, the base comprising InAs channel layer, AlSb layer above the channel layer, In.sub.x Al.sub.1-x As.sub.y Sb.sub.1-y layer containing at least In, Al, and As disposed above the AlSb channel layer, InAs cap layer disposed above and in contact with the In.sub.x Al.sub.1-x As.sub.y Sb.sub.1-y layer disposed below the InAs channel layer and in contact with the substrate, p.sup.+ GaSb layer disposed within the AlSb layer, Schottky gate with a pad disposed on and in contact with the In.sub.x Al.sub.1-x As.sub.y Sb.sub.1-y layer, at least one ohmic contact disposed on the InAs cap layer, and a trench extending through the base to the substrate isolating the gate bonding pad from the device and providing a gate air bridge which prevents contact between the gate and the InAs layer. The gate air bridge fabrication is accomplished by a liquid etchant containing more than half, on volume basis, of concentrated lactic acid or acetic acid with remainder hydrogen peroxide and concentrated hydrofluoric acid. The etchant attacks InAs, In.sub.x Al.sub.1-x As.sub.y Sb.sub.1-y, AlSb, and GaSb but does not attack GaAs and Au-based alloys.

    摘要翻译： 一种电子器件，其特征在于具有GaAs衬底和设置在衬底上的基极，所述基底包括InAs沟道层，在沟道层上方的AlSb层，InxAl1-xAsySb1-y层至少包含位于AlSb沟道上方的In，Al和As 层InAs覆盖层设置在InAs1沟道层下方并与衬底接触的In x Al 1-x As y Sb 1-y层上方并与之接触，设置在AlSb层内的p + GaSb层，具有布置在并且接触的焊盘的肖特基栅极 与InxAl1-xAsySb1-y层，设置在InAs覆盖层上的至少一个欧姆接触，以及延伸穿过基底到衬底的沟槽，将栅极焊盘与器件隔离，并提供栅极空气桥， 门和InAs层。 门空气桥的制造是通过液体蚀刻剂来实现的，该液体蚀刻剂含有一半以上的体积基础上的浓缩乳酸或乙酸，剩余的是过氧化氢和浓缩的氢氟酸。 蚀刻剂攻击InAs，InxAl1-xAsySb1-y，AlSb和GaSb，但不会侵蚀GaAs和Au基合金。

    Low-Resistivity p-Type GaSb Quantum Wells for Low-Power Electronic Devices
    5.
    发明申请
    Low-Resistivity p-Type GaSb Quantum Wells for Low-Power Electronic Devices 审中-公开
    低功耗电子器件的低电阻率p型GaSb量子阱

    公开(公告)号：US20140339501A1

    公开(公告)日：2014-11-20

    申请号：US13895388

    申请日：2013-05-16

    申请人： Brian R. Bennett ,  Theresa F. Chick ,  Mario G. Ancona ,  John Bradley Boos

    发明人： Brian R. Bennett ,  Theresa F. Chick ,  Mario G. Ancona ,  John Bradley Boos

    IPC分类号： H01L29/12

    CPC分类号： H01L29/122 ,  H01L29/201 ,  H01L29/7783

    摘要： A semiconductor device including a heterostructure having at least one low-resistivity p-type GaSb quantum well is provided. The heterostructure includes a layer of InwAl1−wAs on a semi-insulating (100) InP substrate, where the InwAl1−wAs is lattice matched to InP, followed by an AlAsxSb1−x buffer layer on the InwAl1−wAs layer, an AlAsxSb1−x spacer layer on the buffer layer, a GaSb quantum well layer on the spacer layer, an AlAsxSb1−x barrier layer on the quantum well layer, an InyAl1−ySb layer on the barrier layer, and an InAs cap. The semiconductor device is suitable for use in low-power electronic devices such as field-effect transistors.

    摘要翻译： 提供包括具有至少一个低电阻率p型GaSb量子阱的异质结构的半导体器件。 异质结构包括在半绝缘（100）InP衬底上的InwAl1-wAs层，其中InwAl1-wAs与InP晶格匹配，随后是InwAl1-wAs层上的AlAsxSb1-x缓冲层，AlAsxSb1-x 缓冲层上的间隔层，间隔层上的GaSb量子阱层，量子阱层上的AlAs x Sb 1-x势垒层，势垒层上的In y Al 1-y Sb层和InAs帽。 半导体器件适用于诸如场效应晶体管的低功率电子器件。

    n- and p-Channel Field Effect Transistors with Single Quantum Well for Complementary Circuits
    9.
    发明申请
    n- and p-Channel Field Effect Transistors with Single Quantum Well for Complementary Circuits 有权
    具有单量子阱的n沟道场效应晶体管和p沟道场效应晶体管用于互补电路

    公开(公告)号：US20130149845A1

    公开(公告)日：2013-06-13

    申请号：US13756566

    申请日：2013-02-01

    申请人： Brian R. Bennett ,  John Bradley Boos ,  Mario Ancona ,  James G. Champlain ,  Nicolas A. Papanicolaou

    发明人： Brian R. Bennett ,  John Bradley Boos ,  Mario Ancona ,  James G. Champlain ,  Nicolas A. Papanicolaou

    IPC分类号： H01L21/02

    CPC分类号： H01L21/02398 ,  H01L21/02395 ,  H01L21/02466 ,  H01L21/02505 ,  H01L21/02549 ,  H01L27/0605

    摘要： A complementary metal oxide semiconductor (CMOS) device in which a single InxGa1-xSb quantum well serves as both an n-channel and a p-channel in the same device and a method for making the same. The InxGa1-xSb layer is part of a heterostructure that includes a Te-delta doped AlyGa1-ySb layer above the InxGa1-xSb layer on a portion of the structure. The portion of the structure without the Te-delta doped AlyGa1-ySb barrier layer can be fabricated into a p-FET by the use of appropriate source, gate, and drain terminals, and the portion of the structure retaining the Te-delta doped AlyGa1-ySb layer can be fabricated into an n-FET so that the structure forms a CMOS device, wherein the single InxGa1-xSb quantum well serves as the transport channel for both the n-FET portion and the p-FET portion of the heterostructure.

    摘要翻译： 在同一器件中单个In x Ga 1-x Sb量子阱用作n沟道和p沟道的互补金属氧化物半导体（CMOS）器件及其制造方法。 In x Ga 1-x Sb层是异质结构的一部分，其在结构的一部分上包括在In x Ga 1-x Sb层上方的Te-δ掺杂的Al y Ga 1-y Sb。 可以通过使用适当的源极，栅极和漏极端子将不具有Te-δ掺杂的AlI y Ga 1-y Sb阻挡层的部分结构制成p-FET，并且保留Te-δ掺杂的Al y Ga 1 -ySb层可以制造成n-FET，使得该结构形成CMOS器件，其中单个In x Ga 1-x Sb量子阱用作异质结构的n-FET部分和p-FET部分的传输沟道。

    N-and P-Channel Field-Effect Transistors with Single Quantum Well for Complementary Circuits
    10.
    发明申请
    N-and P-Channel Field-Effect Transistors with Single Quantum Well for Complementary Circuits 有权
    具有单量子阱的N沟道场效应晶体管和P沟道场效应晶体管用于互补电路

    公开(公告)号：US20110297916A1

    公开(公告)日：2011-12-08

    申请号：US13115453

    申请日：2011-05-25

    申请人： Brian R. Bennett ,  John Bradley Boos ,  Mario Ancona ,  James G. Champlain ,  Nicolas A. Papanicolaou

    发明人： Brian R. Bennett ,  John Bradley Boos ,  Mario Ancona ,  James G. Champlain ,  Nicolas A. Papanicolaou

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/02398 ,  H01L21/02395 ,  H01L21/02466 ,  H01L21/02505 ,  H01L21/02549 ,  H01L27/0605

    摘要： A complementary metal oxide semiconductor (CMOS) device in which a single InxGa1-xSb quantum well serves as both an n-channel and a p-channel in the same device and a method for making the same. The InxGa1-xSb layer is part of a heterostructure that includes a Te-delta doped AlyGa1-ySb layer above the InxGa1-xSb layer on a portion of the structure. The portion of the structure without the Te-delta doped AlyGa1-ySb barrier layer can be fabricated into a p-FET by the use of appropriate source, gate, and drain terminals, and the portion of the structure retaining the Te-delta doped AlyGa1-ySb layer can be fabricated into an n-FET so that the structure forms a CMOS device, wherein the single InxGa1-xSb quantum well serves as the transport channel for both the n-FET portion and the p-FET portion of the heterostructure.

    摘要翻译： 在同一器件中单个In x Ga 1-x Sb量子阱用作n沟道和p沟道的互补金属氧化物半导体（CMOS）器件及其制造方法。 In x Ga 1-x Sb层是异质结构的一部分，其在结构的一部分上包括在In x Ga 1-x Sb层上方的Te-δ掺杂的Al y Ga 1-y Sb。 可以通过使用适当的源极，栅极和漏极端子将不具有Te-δ掺杂的AlI y Ga 1-y Sb阻挡层的部分结构制成p-FET，并且保留Te-δ掺杂的Al y Ga 1 -ySb层可以制造成n-FET，使得该结构形成CMOS器件，其中单个In x Ga 1-x Sb量子阱用作异质结构的n-FET部分和p-FET部分的传输沟道。