公开(公告)号：US20050054156A1

公开(公告)日：2005-03-10

申请号：US10605128

申请日：2003-09-10

申请人： John Bruley ,  Kevin Chan ,  Paul Kirsch ,  Dae-Gyu Park

发明人： John Bruley ,  Kevin Chan ,  Paul Kirsch ,  Dae-Gyu Park

IPC分类号： C23C16/34 ,  H01L21/02 ,  H01L21/8242

CPC分类号： H01L21/02271 ,  C23C16/345 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/02334 ,  H01L21/3185 ,  H01L28/40

摘要： A method of fabricating a capacitor including an ultra-high vacuum chemical vapor deposition (UHVCVD) step to generate a top-side barrier film layer including silicon nitride at monolayer quantities, and a capacitor so formed, are disclosed. The UHVCVD step allows silicon nitride to be deposited with monolayer level control, and is more successful at placing the nitrogen near the top surface independent of the base film thickness. The resulting capacitor exhibits thermal stability and meets leakage targets after, for example, an approximately 1050° C. thermal treatment. In addition, the UHVCVD nitride step allows for an in situ thermal clean and simpler process control because the reaction is thermally driven.

摘要翻译： 公开了一种制造包括超高真空化学气相沉积（UHVCVD）步骤的电容器的方法，以生成包括单层量的氮化硅的顶侧阻挡膜层和如此形成的电容器。 UHVCVD步骤允许氮化硅沉积单层水平控制，并且在顶部表面附近放置氮而与基膜厚度无关的情况下更为成功。 所得到的电容器在例如约1050℃热处理之后具有热稳定性并满足泄漏目标。 此外，UHVCVD氮化物步骤允许原位热清洁和更简单的过程控制，因为反应是热驱动的。

公开(公告)号：US08643061B2

公开(公告)日：2014-02-04

申请号：US12908024

申请日：2010-10-20

申请人： Haizhou Yin ,  Dae-Gyu Park ,  Oleg Gluschenkov ,  Zhijiong Luo ,  Dominic Schepis ,  Jun Yuan

发明人： Haizhou Yin ,  Dae-Gyu Park ,  Oleg Gluschenkov ,  Zhijiong Luo ,  Dominic Schepis ,  Jun Yuan

IPC分类号： H01L29/66

CPC分类号： H01L21/84 ,  H01L21/76254 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66651 ,  H01L29/78

摘要： A semiconductor structure is provided. The structure includes an n-type field-effect-transistor (NFET) being formed directly on top of a strained silicon layer, and a p-type field-effect-transistor (PFET) being formed on top of the same stained silicon layer but via a layer of silicon-germanium (SiGe). The strained silicon layer may be formed on top of a layer of insulating material or a silicon-germanium layer with graded Ge content variation. Furthermore, the NFET and PFET are formed next to each other and are separated by a shallow trench isolation (STI) formed inside the strained silicon layer. Methods of forming the semiconductor structure are also provided.

摘要翻译： 提供半导体结构。 该结构包括直接形成在应变硅层的顶部上的n型场效应晶体管（NFET），以及形成在同一染色硅层顶部的p型场效应晶体管（PFET），但是 通过一层硅 - 锗（SiGe）。 应变硅层可以形成在具有分级Ge含量变化的绝缘材料层或硅 - 锗层的顶部上。 此外，NFET和PFET彼此相邻形成，并且通过形成在应变硅层内部的浅沟槽隔离（STI）分开。 还提供了形成半导体结构的方法。

公开(公告)号：US08557652B2

公开(公告)日：2013-10-15

申请号：US13608422

申请日：2012-09-10

申请人： Oleg Gluschenkov ,  Dae-Gyu Park ,  Haizhou Yin

发明人： Oleg Gluschenkov ,  Dae-Gyu Park ,  Haizhou Yin

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857

摘要： Semiconductor structures including a high k gate dielectric material that has at least one surface threshold voltage adjusting region located within 3 nm or less from an upper surface of the high k gate dielectric are provided. The at least one surface threshold voltage adjusting region is formed by a cluster beam implant step in which at least one threshold voltage adjusting impurity is formed directly within the high k gate dielectric or driven in from an overlying threshold voltage adjusting material which is subsequently removed from the structure following the cluster beam implant step.

公开(公告)号：US20130019944A1

公开(公告)日：2013-01-24

申请号：US13188214

申请日：2011-07-21

申请人： Bahman Hekmatshoar-Tabari ,  Marinus Hopstaken ,  Dae-Gyu Park ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Bahman Hekmatshoar-Tabari ,  Marinus Hopstaken ,  Dae-Gyu Park ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L31/0376

CPC分类号： H01L31/03762 ,  H01L31/02167 ,  H01L31/075 ,  H01L31/1864 ,  H01L31/202 ,  Y02E10/548 ,  Y02P70/521

摘要： A method of forming a semiconductor material of a photovoltaic device that includes providing a surface of a hydrogenated amorphous silicon containing material, and annealing the hydrogenated amorphous silicon containing material in a deuterium containing atmosphere. Deuterium from the deuterium-containing atmosphere is introduced to the lattice of the hydrogenated amorphous silicon containing material through the surface of the hydrogenated amorphous silicon containing material. In some embodiments, the deuterium that is introduced to the lattice of the hydrogenated amorphous silicon containing material increases the stability of the hydrogenated amorphous silicon containing material.

公开(公告)号：US20120187502A1

公开(公告)日：2012-07-26

申请号：US13432716

申请日：2012-03-28

申请人： Oleg Gluschenkov ,  Dae-Gyu Park ,  Haizhou Yin

发明人： Oleg Gluschenkov ,  Dae-Gyu Park ,  Haizhou Yin

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823857

摘要： Semiconductor structures including a high k gate dielectric material that has at least one surface threshold voltage adjusting region located within 3 nm or less from an upper surface of the high k gate dielectric are provided. The at least one surface threshold voltage adjusting region is formed by a cluster beam implant step in which at least one threshold voltage adjusting impurity is formed directly within the high k gate dielectric or driven in from an overlying threshold voltage adjusting material which is subsequently removed from the structure following the cluster beam implant step.

摘要翻译： 提供了包括高k栅介质材料的半导体结构，其具有位于距离高k栅极电介质的上表面3nm以内的至少一个表面阈值电压调整区域。 所述至少一个表面阈值电压调整区域通过聚束射束注入步骤形成，其中至少一个阈值电压调节杂质直接形成在所述高k栅极电介质内或从上限的阈值电压调节材料驱动，所述材料随后从 聚束束植入步骤后的结构。

公开(公告)号：US08030716B2

公开(公告)日：2011-10-04

申请号：US12883874

申请日：2010-09-16

申请人： Dae-Gyu Park ,  Michael P. Chudzik ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Dae-Gyu Park ,  Michael P. Chudzik ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L21/70

CPC分类号： H01L21/823842 ,  H01L21/823857 ,  H01L29/785

摘要： A method for fabricating a CMOS structure is disclosed. The method includes the blanket disposition of a high-k gate insulator layer in an NFET device and in a PFET device, and the implementation of a gate metal layer over the NFET device. This is followed by a blanket disposition of an Al layer over both the NFET device and the PFET device. The method further involves a blanket disposition of a shared gate metal layer over the Al layer. When the PFET device is exposed to a thermal annealing, the high-k dielectric oxidizes the Al layer, thereby turning the Al layer into a PFET interfacial control layer, while in the NFET device the Al becomes a region of the metal gate.

摘要翻译： 公开了一种用于制造CMOS结构的方法。 该方法包括在NFET器件和PFET器件中的高k栅极绝缘体层的覆盖布置以及NFET器件上的栅极金属层的实现。 之后是在NFET器件和PFET器件上的Al层的覆盖布置。 该方法还包括在Al层上共享的栅极金属层的布置布置。 当PFET器件暴露于热退火时，高k电介质氧化Al层，从而将Al层转变为PFET界面控制层，而在NFET器件中，Al成为金属栅极的一个区域。

公开(公告)号：US07989298B1

公开(公告)日：2011-08-02

申请号：US12692859

申请日：2010-01-25

申请人： Kevin K. Chan ,  Brian J. Greene ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Thomas S. Kanarsky ,  Jophy S. Koshy ,  Kevin McStay ,  Dae-Gyu Park ,  Johan W. Weijtmans ,  Frank B. Yang

发明人： Kevin K. Chan ,  Brian J. Greene ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Thomas S. Kanarsky ,  Jophy S. Koshy ,  Kevin McStay ,  Dae-Gyu Park ,  Johan W. Weijtmans ,  Frank B. Yang

IPC分类号： H01L21/336 ,  H01L21/76

CPC分类号： H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses. Then the dummy spacers are removed and the transistor can be completed by forming source/drain regions of the transistor that are at least partially disposed in the stressed semiconductor material regions.

摘要翻译： 提供半导体器件和制造该器件的方法。 该方法可以包括形成覆盖在单晶半导体区域的主表面上的栅极导体并且在栅极导体的暴露的壁上形成第一间隔物。 使用栅极导体和第一间隔物作为掩模，至少延伸区域注入到半导体区域中，并且形成从第一间隔物向外延伸的虚设间隔物。 使用虚拟间隔件作为掩模，半导体区域被蚀刻以形成具有从主表面向底表面向下延伸的至少基本上直的壁的凹槽，使得在底表面和壁之间限定大的角度。 随后，通过在凹槽内外延生长应力单晶半导体材料的区域来继续该过程。 然后去除虚拟间隔物，并且可以通过形成至少部分地设置在受应力的半导体材料区域中的晶体管的源极/漏极区域来完成晶体管。

公开(公告)号：US20110183486A1

公开(公告)日：2011-07-28

申请号：US12692859

申请日：2010-01-25

申请人： Kevin K. Chan ,  Brian J. Greene ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Thomas S. Kanarsky ,  Jophy S. Koshy ,  Kevin McStay ,  Dae-Gyu Park ,  Johan W. Weijtmans ,  Frank B. Yang

发明人： Kevin K. Chan ,  Brian J. Greene ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Thomas S. Kanarsky ,  Jophy S. Koshy ,  Kevin McStay ,  Dae-Gyu Park ,  Johan W. Weijtmans ,  Frank B. Yang

IPC分类号： H01L21/336

CPC分类号： H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses. Then the dummy spacers are removed and the transistor can be completed by forming source/drain regions of the transistor that are at least partially disposed in the stressed semiconductor material regions.

摘要翻译： 提供半导体器件和制造该器件的方法。 该方法可以包括形成覆盖在单晶半导体区域的主表面上的栅极导体并且在栅极导体的暴露的壁上形成第一间隔物。 使用栅极导体和第一间隔物作为掩模，至少延伸区域注入到半导体区域中，并且形成从第一间隔物向外延伸的虚设间隔物。 使用虚拟间隔件作为掩模，半导体区域被蚀刻以形成具有从主表面向底表面向下延伸的至少基本上直的壁的凹槽，使得在底表面和壁之间限定大的角度。 随后，通过在凹槽内外延生长应力单晶半导体材料的区域来继续该过程。 然后去除虚拟间隔物，并且可以通过形成至少部分地设置在受应力的半导体材料区域中的晶体管的源极/漏极区域来完成晶体管。

公开(公告)号：US07947549B2

公开(公告)日：2011-05-24

申请号：US12037158

申请日：2008-02-26

申请人： Dae-Gyu Park ,  Michael P Chudzik ,  Rashmi Jha ,  Siddarth A Krishnan ,  Naim Moumen ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Dae-Gyu Park ,  Michael P Chudzik ,  Rashmi Jha ,  Siddarth A Krishnan ,  Naim Moumen ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/823842 ,  H01L29/785

摘要： CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed.

摘要翻译： 公开了CMOS电路结构，其中PFET和NFET器件具有由相同的栅极绝缘体材料构成的高k电介质层以及由相同栅极金属材料组成的金属栅极层。 PFET器件具有能够沿p方向移动栅极的有效功能的“p”接口控制层。 在本发明的代表性实施例中，“p”界面控制层是氧化铝。 NFET器件可以具有“n”个界面控制层。 “p”和“n”界面控制层的材料是不同的材料。 “p”和“n”界面控制层位于其相应的高k电介质层的相对侧。 还公开了制造具有相对定位的“p”和“n”界面控制层的CMOS电路结构的方法。

公开(公告)号：US20110089495A1

公开(公告)日：2011-04-21

申请号：US12582139

申请日：2009-10-20

申请人： Oleg Gluschenkov ,  Dae-Gyu Park ,  Haizhou Yin

发明人： Oleg Gluschenkov ,  Dae-Gyu Park ,  Haizhou Yin

IPC分类号： H01L29/66 ,  H01L21/8238

CPC分类号： H01L21/823857

摘要： Semiconductor structures including a high k gate dielectric material that has at least one surface threshold voltage adjusting region located within 3 nm or less from an upper surface of the high k gate dielectric are provided. The at least one surface threshold voltage adjusting region is formed by a cluster beam implant step in which at least one threshold voltage adjusting impurity is formed directly within the high k gate dielectric or driven in from an overlying threshold voltage adjusting material which is subsequently removed from the structure following the cluster beam implant step.

摘要翻译： 提供了包括高k栅介质材料的半导体结构，其具有位于距离高k栅极电介质的上表面3nm以内的至少一个表面阈值电压调整区域。 所述至少一个表面阈值电压调整区域通过聚束射束注入步骤形成，其中至少一个阈值电压调节杂质直接形成在所述高k栅极电介质内或从上限的阈值电压调节材料驱动，所述材料随后从 聚束束植入步骤后的结构。