利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

9 条记录 (耗时 0.026 秒)

    Methods and apparatus for transporting narrowband (voice) traffic over a broadband (ATM) network
    1.
    发明授权
    Methods and apparatus for transporting narrowband (voice) traffic over a broadband (ATM) network 有权
    通过宽带（ATM）网络传输窄带（语音）业务的方法和装置

    公开(公告)号：US06282191B1

    公开(公告)日：2001-08-28

    申请号：US09371196

    申请日：1999-08-10

    申请人： John Cumberton ,  Pasquale Cassella ,  Ramanathan Ramanathan ,  Michael McLoughlin ,  Xing Chen

    发明人： John Cumberton ,  Pasquale Cassella ,  Ramanathan Ramanathan ,  Michael McLoughlin ,  Xing Chen

    IPC分类号： H04M700

    CPC分类号： H04L29/06 ,  H04L12/4633 ,  H04L12/5601 ,  H04L12/66 ,  H04L69/08 ,  H04L2012/563 ,  H04L2012/5663 ,  H04M7/063 ,  H04M7/1205

    摘要： A SS7 signalling router receives SS7 signalling regarding narrowband calls to be routed over the ATM network. When the SS7 router receives signalling from the SS7 network, it does not process the signalling, but reads the originator point code (OPC) and forwards the signalling via the ATM network to the ATM switch which is attached to the originator of the message. An interworking function (IWF) at the ATM switch processes the SS7 signalling by generating the appropriate ATM signalling to set up a circuit between the originating ATM switch and the destination ATM switch. The IWF at the originating ATM switch also processes the SS7 signalling by returning it to the SS7 router with the destination point code (DPC) of the PSTN switch coupled to the destination ATM switch. When the SS7 router receives an SS7 signalling message from an ATM switch, it forwards it to the SS7 network where it is sent to the DPC. The IWF at each ATM switch is preferably distributed among several processors including a signalling VSM controller (an SVSM), a plurality of VSM controllers and an ISUP controller. SS7 SUs enter the SVSM controller which separates MSUs from FISUs and LSSUs. The MSUs are sent to the ISUP controller which interrogates the CIC of the IAM messages and forwards the IAM information to the appropriate VSM controller for narrowband to broadband conversion.

    摘要翻译： SS7信令路由器接收关于通过ATM网络路由的窄带呼叫的SS7信令。 当SS7路由器从SS7网络接收到信令时，它不处理信令，而是读取发起方点号码（OPC），并通过ATM网络将信令转发到附加到消息发起者的ATM交换机。 ATM交换机上的互通功能（IWF）通过生成适当的ATM信令来处理SS7信令，以在始发ATM交换机和目的ATM交换机之间建立电路。 始发ATM交换机上的IWF还通过将PSTN交换机的目的地点码（DPC）耦合到目的地ATM交换机将其返回到SS7路由器来处理SS7信令。 当SS7路由器从ATM交换机接收到SS7信令消息时，将其转发到SS7网络，并将其发送到DPC。 每个ATM交换机上的IWF优选地分布在包括信令VSM控制器（SVSM），多个VSM控制器和ISUP控制器的若干处理器中。 SS7 SU进入SVM控制器，将MSU与FISU和LSSU分离。 MSU被发送到询问IAM消息的CIC的ISUP控制器，并将IAM信息转发到适当的VSM控制器以进行窄带到宽带转换。

    Coordinated recalibration of high bandwidth memories in a multiprocessor computer
    5.
    发明授权
    Coordinated recalibration of high bandwidth memories in a multiprocessor computer 有权
    多处理器计算机中高带宽存储器的协调重新校准

    公开(公告)号：US06874102B2

    公开(公告)日：2005-03-29

    申请号：US09799478

    申请日：2001-03-05

    申请人： John W. Doody ,  Finbarr Denis Long ,  Michael McLoughlin ,  Michael James O'Keefe

    发明人： John W. Doody ,  Finbarr Denis Long ,  Michael McLoughlin ,  Michael James O'Keefe

    IPC分类号： G06F11/00 ,  G06F11/16

    CPC分类号： G06F11/1691

    摘要： Methods and apparatus for implementing high-bandwidth memory subsystems in a multiprocessor computing environment. Each component in the memory subsystem has a recalibration procedure. The computer provides a low-frequency clock signal with a period substantially equal to the duration between recalibration cycles of the components of the memory subsystem. Transitions in the low-frequency clock signal initiate a deterministically-determined delay. Lapse of the delay in turn triggers the recalibration of the components of the memory subsystem, ensuring synchronous recalibration. Synchronizing the recalibration procedures minimizes the unavailability of the memory subsystems, consequently reducing voting errors between CPUs.

    摘要翻译： 在多处理器计算环境中实现高带宽存储器子系统的方法和装置。 存储器子系统中的每个组件都具有重新校准程序。 计算机提供低频时钟信号，其周期基本上等于存储器子系统的组件的重新校准周期之间的持续时间。 低频时钟信号中的转换启动确定性确定的延迟。 延迟的延迟反过来触发了内存子系统组件的重新校准，确保同步重新校准。 同步重新校准程序可以最大限度地减少内存子系统的不可用性，从而减少CPU之间的投票错误。

    Methods and apparatus for generating high-frequency clocks deterministically from a low-frequency system reference clock
    6.
    发明授权
    Methods and apparatus for generating high-frequency clocks deterministically from a low-frequency system reference clock 有权
    从低频系统参考时钟确定性地产生高频时钟的方法和装置

    公开(公告)号：US06813721B1

    公开(公告)日：2004-11-02

    申请号：US09665887

    申请日：2000-09-20

    申请人： Mark Tetreault ,  Michael McLoughlin ,  Jeffrey Somers

    发明人： Mark Tetreault ,  Michael McLoughlin ,  Jeffrey Somers

    IPC分类号： G06F112

    CPC分类号： G06F1/10

    摘要： A method and apparatus for maintaining clock phase alignment among system modules of a fault-tolerant computing system. In one embodiment, a low-frequency system reference clock signal is distributed to all system modules where it is multiplied to generate higher-frequency local clock signals. All local clock signals are then synchronized to the rising edge of the reference clock signal and the first rising edge in relation to a timing event is also identified.

    摘要翻译： 一种用于在容错计算系统的系统模块之间维持时钟相位对准的方法和装置。 在一个实施例中，低频系统参考时钟信号被分配到所有系统模块，在该系统模块被相乘以产生较高频率的本地时钟信号。 然后，所有本地时钟信号被同步到参考时钟信号的上升沿，并且还识别与定时事件相关的第一上升沿。

    Apparatus and method for accessing a mass storage device in a fault-tolerant server
    7.
    发明授权
    Apparatus and method for accessing a mass storage device in a fault-tolerant server 有权
    用于访问容错服务器中的大容量存储设备的装置和方法

    公开(公告)号：US06971043B2

    公开(公告)日：2005-11-29

    申请号：US09832467

    申请日：2001-04-11

    申请人： Michael McLoughlin ,  Gerry Griffin

    发明人： Michael McLoughlin ,  Gerry Griffin

    IPC分类号： G06F11/07 ,  G06F11/20 ,  H04L1/22 ,  G06F11/00

    CPC分类号： G06F11/2007 ,  G06F11/0727 ,  G06F11/079 ,  G06F11/1641 ,  G06F11/165 ,  G06F11/184 ,  G06F11/2005 ,  H04L1/22

    摘要： An apparatus and method for accessing a first local mass storage device or a second local mass storage device in a fault-tolerant server. In one embodiment, the fault-tolerant server establishes communication between a first computing element and a first local mass storage device. The fault-tolerant server also establishes communications between a second computing element and a second local mass storage device. In one embodiment, the first computing element and the second computing element issue substantially similar instruction streams to one of the local mass storage devices.

    摘要翻译： 一种用于访问容错服务器中的第一本地大容量存储设备或第二本地大容量存储设备的设备和方法。 在一个实施例中，容错服务器建立第一计算元件与第一本地大容量存储设备之间的通信。 容错服务器还建立第二计算元件与第二本地大容量存储设备之间的通信。 在一个实施例中，第一计算元件和第二计算元件向本地大容量存储设备之一发出基本相似的指令流。

    Apparatus and method for two computing elements in a fault-tolerant server to execute instructions in lockstep
    8.
    发明授权
    Apparatus and method for two computing elements in a fault-tolerant server to execute instructions in lockstep 有权
    容错服务器中的两个计算元素的装置和方法，用于在锁步骤中执行指令

    公开(公告)号：US06928583B2

    公开(公告)日：2005-08-09

    申请号：US09832466

    申请日：2001-04-11

    申请人： Gerry Griffin ,  Michael McLoughlin

    发明人： Gerry Griffin ,  Michael McLoughlin

    IPC分类号： G06F11/00 ,  G06F11/22

    CPC分类号： G06F11/1645 ,  G06F11/1675

    摘要： An apparatus and method for a first computing element and a second computing element to execute in lockstep in a fault-tolerant server. In one embodiment, the first computing element provides a first instruction to a communications link and the second computing element provides a second instruction to a communications link. In one embodiment, a first local input-output (I/O) subsystem and a second local I/O subsystem are each in communication with the communications link. The first and/or the second local I/O subsystem compare the first instruction and the second instruction. In one embodiment, the first and second local I/O subsystems indicate a fault of the first computing element or the second computing element. Such a fault may be determined by a miscompare of the first instruction and the second instruction.

    摘要翻译： 一种用于第一计算元件和第二计算元件在容错服务器中的锁步执行的装置和方法。 在一个实施例中，第一计算元件向通信链路提供第一指令，并且第二计算元件向通信链路提供第二指令。 在一个实施例中，第一本地输入输出（I / O）子系统和第二本地I / O子系统各自与通信链路通信。 第一和/或第二本地I / O子系统比较第一条指令和第二条指令。 在一个实施例中，第一和第二本地I / O子系统指示第一计算元件或第二计算元件的故障。 这种故障可以通过第一指令和第二指令的误比较来确定。