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    DYNAMIC RANDOM ACCESS MEMORY CIRCUIT, DESIGN STRUCTURE AND METHOD
    1.
    发明申请
    DYNAMIC RANDOM ACCESS MEMORY CIRCUIT, DESIGN STRUCTURE AND METHOD 有权
    动态随机访问存储器电路，设计结构和方法

    公开(公告)号：US20090268510A1

    公开(公告)日：2009-10-29

    申请号：US12108548

    申请日：2008-04-24

    申请人： John E. Barth, JR. ,  Kangguo Cheng ,  Hoki Kim ,  Geng Wang

    发明人： John E. Barth, JR. ,  Kangguo Cheng ,  Hoki Kim ,  Geng Wang

    IPC分类号： G11C11/24 ,  H01L21/8242

    CPC分类号： H01L27/10829 ,  G11C7/02 ,  G11C11/4099 ,  H01L27/10861 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10897

    摘要： Disclosed is a DRAM circuit that incorporates an improved reference cell, has half the capacitance of the memory cell, does not require a particular reference voltage, and can be formed using the same fabrication processes as the memory cell. This DRAM circuit comprises a memory cell with a single trench capacitor and a reference cell having two trench capacitors. The two reference cell trench capacitors are connected in series through a merged buried capacitor plate such that they provide half the capacitance of the memory cell trench capacitor. Additionally, the reference cell trench capacitors have essentially the same structure as the memory cell trench capacitor so that they can be formed in conjunction with the memory cell trench capacitor. Also disclosed are a design structure for the above-described memory circuit and a method for forming the above-described memory circuit.

    摘要翻译： 公开了一种DRAM电路，其包含改进的参考单元，具有存储单元的一半电容，不需要特定参考电压，并且可以使用与存储单元相同的制造工艺来形成。 该DRAM电路包括具有单沟槽电容器的存储单元和具有两个沟槽电容器的参考单元。 两个参考单元沟槽电容器通过合并的埋入式电容器板串联连接，使得它们提供存储单元沟槽电容器的一半的电容。 此外，参考单元沟槽电容器具有与存储单元沟槽电容器基本相同的结构，使得它们可以与存储单元沟槽电容器结合形成。 还公开了用于上述存储电路的设计结构和用于形成上述存储电路的方法。

    INTEGRATED CIRCUITS COMPRISING AN ACTIVE TRANSISTOR ELECTRICALLY CONNECTED TO A TRENCH CAPACITOR BY AN OVERLYING CONTACT
    2.
    发明申请
    INTEGRATED CIRCUITS COMPRISING AN ACTIVE TRANSISTOR ELECTRICALLY CONNECTED TO A TRENCH CAPACITOR BY AN OVERLYING CONTACT 有权
    集成电路，包含通过过度接触电路连接到TRENCH电容器的有源晶体管

    公开(公告)号：US20120205732A1

    公开(公告)日：2012-08-16

    申请号：US13454635

    申请日：2012-04-24

    申请人： John E. Barth, JR. ,  Kangguo Cheng ,  Michael Sperling ,  Geng Wang

    发明人： John E. Barth, JR. ,  Kangguo Cheng ,  Michael Sperling ,  Geng Wang

    IPC分类号： H01L27/108

    CPC分类号： H01L21/76895 ,  H01L23/485 ,  H01L27/10867 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit includes an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; a passive transistor laterally spaced from the active transistor, wherein at least a portion of the trench capacitor is interposed between the active and passive transistors; an interlevel dielectric disposed upon the active and passive transistors; and a first conductive contact extending through the interlevel dielectric to the drain junction of the active transistor and the at least a portion of the trench capacitor between the active and passive transistors, wherein the first conductive contact electrically connects the trench capacitor to the drain junction of the active transistor.

    摘要翻译： 集成电路包括与形成在半导体衬底中的沟槽电容器横向相邻的有源晶体管，所述有源晶体管包括源极结和漏极结，其中阻挡层沿着所述沟槽电容器的外围设置以隔离所述沟槽电容器; 与有源晶体管横向隔开的无源晶体管，其中所述沟槽电容器的至少一部分插入在所述有源和无源晶体管之间; 布置在有源和无源晶体管上的层间电介质; 以及第一导电接触件，其延伸穿过所述有源晶体管的所述有源晶体管和所述沟槽电容器的所述至少一部分的所述层间电介质的漏极结到所述有源和无源晶体管之间，其中所述第一导电接触将所述沟槽电容器电连接到所述沟道电容器 有源晶体管。

    INTEGRATED CIRCUITS COMPRISING AN ACTIVE TRANSISTOR ELECTRICALLY CONNECTED TO A TRENCH CAPACITOR BY AN OVERLYING CONTACT AND METHODS OF MAKING
    3.
    发明申请
    INTEGRATED CIRCUITS COMPRISING AN ACTIVE TRANSISTOR ELECTRICALLY CONNECTED TO A TRENCH CAPACITOR BY AN OVERLYING CONTACT AND METHODS OF MAKING 有权
    包含通过过度接触电路连接到TRENCH电容器的有源晶体管的集成电路和制造方法

    公开(公告)号：US20100032742A1

    公开(公告)日：2010-02-11

    申请号：US12186780

    申请日：2008-08-06

    申请人： John E. Barth, JR. ,  Kangguo Cheng ,  Michael Sperling ,  Geng Wang

    发明人： John E. Barth, JR. ,  Kangguo Cheng ,  Michael Sperling ,  Geng Wang

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L21/76895 ,  H01L23/485 ,  H01L27/10867 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming an integrated circuit comprises: providing a semiconductor topography comprising an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; forming an interlevel dielectric across the semiconductor topography; concurrently etching (i) a first opening through the interlevel dielectric to the drain junction of the active transistor and the trench capacitor, and (ii) a second opening through the interlevel dielectric to the source junction of the active transistor; and filling the first opening and the second opening with a conductive material to form a strap for electrically connecting the trench capacitor to the drain junction of the active transistor and to also form a contact for electrically connecting the source junction to an overlying level of the integrated circuit.

    摘要翻译： 一种形成集成电路的方法包括：提供半导体形貌，其包括与形成在半导体衬底中的沟槽电容器横向相邻的有源晶体管，所述有源晶体管包括源极结和漏极结，其中阻挡层沿着外围设置 用于隔离沟槽电容器的沟槽电容器; 在半导体形貌上形成层间电介质; 同时蚀刻（i）通过层间电介质到有源晶体管和沟槽电容器的漏极结的第一开口，以及（ii）通过层间电介质到有源晶体管的源极结的第二开口; 以及用导电材料填充第一开口和第二开口以形成用于将沟槽电容器电连接到有源晶体管的漏极结的带，并且还形成用于将源极结连接到集成的上覆层 电路。

    MEMORY DEVICE SUPPORT OF DYNAMICALLY CHANGING FREQUENCY IN MEMORY SYSTEMS
    4.
    发明申请
    MEMORY DEVICE SUPPORT OF DYNAMICALLY CHANGING FREQUENCY IN MEMORY SYSTEMS 审中-公开
    记忆体系中动态变化频率的记忆体设备支持

    公开(公告)号：US20130262792A1

    公开(公告)日：2013-10-03

    申请号：US13431108

    申请日：2012-03-27

    申请人： John E. Barth, JR. ,  Joab D. Henderson ,  Ryan J. Pennington ,  Anuwat Saetow ,  Robert B. Tremaine ,  Kenneth L. Wright

    发明人： John E. Barth, JR. ,  Joab D. Henderson ,  Ryan J. Pennington ,  Anuwat Saetow ,  Robert B. Tremaine ,  Kenneth L. Wright

    IPC分类号： G06F12/00

    CPC分类号： G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

    摘要： An embodiment is a method includes writing a first set of memory device parameters to a first mode register in a memory device, wherein the first set of memory device parameters correspond to a first frequency, monitoring selected parameters for the memory system while the memory device operates at the first frequency and predicting a second frequency that the memory device will operate at subsequent to the first frequency, the predicting being based on the monitored selected parameters. The method further includes writing a second set of memory device parameters to second mode register in the memory device, receiving a frequency change request at a memory controller associated with the memory device, the frequency change request to operate at a new frequency and updating the first mode register with the second set of memory device parameters from the second mode register responsive to the new frequency being equal to the second frequency.

    摘要翻译： 实施例是一种方法，包括将第一组存储器件参数写入存储器件中的第一模式寄存器，其中第一组存储器件参数对应于第一频率，在存储器件操作期间监视存储器系统的选定参数 在第一频率处，并且预测存储器设备将在第一频率之后操作的第二频率，所述预测基于所监视的所选择的参数。 该方法还包括将第二组存储器件参数写入存储器件中的第二模式寄存器，在与存储器件相关联的存储器控​​制器处接收频率改变请求，频率改变请求以新频率操作并更新第一 模式寄存器，响应于新频率等于第二频率，来自第二模式寄存器的第二组存储器件参数。

    VDD PRE-SET OF DIRECT SENSE DRAM
    5.
    发明申请
    VDD PRE-SET OF DIRECT SENSE DRAM 有权
    直流感测DRAM的VDD预置

    公开(公告)号：US20110267916A1

    公开(公告)日：2011-11-03

    申请号：US12770976

    申请日：2010-04-30

    申请人： John E. Barth, JR.

    发明人： John E. Barth, JR.

    IPC分类号： G11C5/14

    CPC分类号： G11C11/4091

    摘要： A direct sense memory array architecture and method of operation includes a plurality of memory cells where a bit-line restore voltage level is optimized to reduce memory cell leakage during a first inactive period, and a bit-line preset voltage level is optimized for signal sensing during a second active period. The architecture includes a sense head having of a pair of cross coupled gated inverters. Each of the gated inverters is responsive to a first and second gate control signal which can independently gate a power supply to the inverter circuit within each gated inverter. During the second active period, a first gated inverter senses the data state on the first bit-line, and a second gated inverter performs a preset and write-back function on the first bit-line.

    摘要翻译： 直接读出存储器阵列结构和操作方法包括多个存储器单元，其中位线恢复电压电平被优化以在第一非活动时段期间减少存储器单元泄漏，并且位线预设电压电平被优化用于信号感测 在第二个活跃期间。 该架构包括具有一对交叉耦合门控反相器的感测头。 每个门控逆变器响应于第一和第二门控制信号，该第一和第二门控制信号可以独立地对每个门控逆变器内的逆变器电路的电源供电。 在第二活动期间，第一选通逆变器检测第一位线上的数据状态，第二门控反相器在第一位线上执行预置和回写功能。

    SOI BODY CONTACT USING E-DRAM TECHNOLOGY
    6.
    发明申请
    SOI BODY CONTACT USING E-DRAM TECHNOLOGY 有权
    SOI身体接触使用电子DRAM技术

    公开(公告)号：US20110177659A1

    公开(公告)日：2011-07-21

    申请号：US13075552

    申请日：2011-03-30

    申请人： John E. Barth, JR. ,  Kerry Bernstein ,  Francis R. White

    发明人： John E. Barth, JR. ,  Kerry Bernstein ,  Francis R. White

    IPC分类号： H01L21/336

    CPC分类号： H01L29/78615

    摘要： A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a body contact disposed under the body/channel region and in the insulator layer. The body contact electrically connects with and contacts with the body/channel region of the semiconductor device and the substrate, to thereby form an ohmic contact and to eliminate floating body effects.

    摘要翻译： 公开了半导体结构。 半导体结构包括有源半导体层，具有设置在有源半导体层顶部的栅极的半导体器件以及设置在有源半导体层内的源极和漏极区域以及主体/沟道区域，具有第一和第二 所述第一侧与所述有源半导体层相邻，与所述绝缘体层的第二侧相邻配置的基板，设置在所述主体/沟道区域的下方以及所述绝缘体层的主体接触部。 体接触与半导体器件和衬底的主体/沟道区域电连接并与其接触，从而形成欧姆接触并消除浮体效应。

    CAPACITIVELY ISOLATED MISMATCH COMPENSATED SENSE AMPLIFIER
    9.
    发明申请
    CAPACITIVELY ISOLATED MISMATCH COMPENSATED SENSE AMPLIFIER 有权
    电容式隔离失调补偿放大器

    公开(公告)号：US20100157698A1

    公开(公告)日：2010-06-24

    申请号：US12343554

    申请日：2008-12-24

    申请人： John E. Barth, JR.

    发明人： John E. Barth, JR.

    IPC分类号： G11C7/06

    CPC分类号： G11C7/065 ,  G11C7/067 ,  G11C11/4091

    摘要： According to an embodiment of the invention, a sense amplifier for, e.g., an array of DRAM data storage cells includes one or more amplifier stages connected together in series. The amplifier stages together form the sense amplifier for the DRAM array. Each amplifier stage includes an isolation capacitor to reduce to a relatively small value any mismatch between the threshold voltages of the transistors within each amplifier stage. A bitline from the DRAM array of memory cells connects to the first amplifier stage. An output from the last amplifier stage connects to a write back switch, the output of which connects to the bitline at the input of the first amplifier stage.

    摘要翻译： 根据本发明的实施例，用于例如DRAM数据存储单元的阵列的读出放大器包括串联连接在一起的一个或多个放大器级。 放大器级一起形成用于DRAM阵列的读出放大器。 每个放大器级包括隔离电容器，以将每个放大器级内的晶体管的阈值电压之间的失配降至相对较小的值。 存储器单元的DRAM阵列的位线连接到第一放大器级。 来自最后一个放大器级的输出端连接到写回开关，其回输开关在第一放大器级的输入处连接到位线。