公开(公告)号：US07668003B2

公开(公告)日：2010-02-23

申请号：US12108548

申请日：2008-04-24

申请人： John E. Barth, Jr. ,  Kangguo Cheng ,  Hoki Kim ,  Geng Wang

发明人： John E. Barth, Jr. ,  Kangguo Cheng ,  Hoki Kim ,  Geng Wang

IPC分类号： G11C11/24

CPC分类号： H01L27/10829 ,  G11C7/02 ,  G11C11/4099 ,  H01L27/10861 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10897

摘要： Disclosed is a DRAM circuit that incorporates an improved reference cell, has half the capacitance of the memory cell, does not require a particular reference voltage, and can be formed using the same fabrication processes as the memory cell. This DRAM circuit comprises a memory cell with a single trench capacitor and a reference cell having two trench capacitors. The two reference cell trench capacitors are connected in series through a merged buried capacitor plate such that they provide half the capacitance of the memory cell trench capacitor. Additionally, the reference cell trench capacitors have essentially the same structure as the memory cell trench capacitor so that they can be formed in conjunction with the memory cell trench capacitor. Also disclosed are a design structure for the above-described memory circuit and a method for forming the above-described memory circuit.

摘要翻译： 公开了一种DRAM电路，其包含改进的参考单元，具有存储单元的一半电容，不需要特定参考电压，并且可以使用与存储单元相同的制造工艺来形成。 该DRAM电路包括具有单沟槽电容器的存储单元和具有两个沟槽电容器的参考单元。 两个参考单元沟槽电容器通过合并的埋入式电容器板串联连接，使得它们提供存储单元沟槽电容器的一半的电容。 此外，参考单元沟槽电容器具有与存储单元沟槽电容器基本相同的结构，使得它们可以与存储单元沟槽电容器结合形成。 还公开了用于上述存储电路的设计结构和用于形成上述存储电路的方法。

公开(公告)号：US20090268510A1

公开(公告)日：2009-10-29

申请号：US12108548

申请日：2008-04-24

申请人： John E. Barth, JR. ,  Kangguo Cheng ,  Hoki Kim ,  Geng Wang

发明人： John E. Barth, JR. ,  Kangguo Cheng ,  Hoki Kim ,  Geng Wang

IPC分类号： G11C11/24 ,  H01L21/8242

CPC分类号： H01L27/10829 ,  G11C7/02 ,  G11C11/4099 ,  H01L27/10861 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10897

摘要： Disclosed is a DRAM circuit that incorporates an improved reference cell, has half the capacitance of the memory cell, does not require a particular reference voltage, and can be formed using the same fabrication processes as the memory cell. This DRAM circuit comprises a memory cell with a single trench capacitor and a reference cell having two trench capacitors. The two reference cell trench capacitors are connected in series through a merged buried capacitor plate such that they provide half the capacitance of the memory cell trench capacitor. Additionally, the reference cell trench capacitors have essentially the same structure as the memory cell trench capacitor so that they can be formed in conjunction with the memory cell trench capacitor. Also disclosed are a design structure for the above-described memory circuit and a method for forming the above-described memory circuit.

摘要翻译： 公开了一种DRAM电路，其包含改进的参考单元，具有存储单元的一半电容，不需要特定参考电压，并且可以使用与存储单元相同的制造工艺来形成。 该DRAM电路包括具有单沟槽电容器的存储单元和具有两个沟槽电容器的参考单元。 两个参考单元沟槽电容器通过合并的埋入式电容器板串联连接，使得它们提供存储单元沟槽电容器的一半的电容。 此外，参考单元沟槽电容器具有与存储单元沟槽电容器基本相同的结构，使得它们可以与存储单元沟槽电容器结合形成。 还公开了用于上述存储电路的设计结构和用于形成上述存储电路的方法。

公开(公告)号：US20120205732A1

公开(公告)日：2012-08-16

申请号：US13454635

申请日：2012-04-24

申请人： John E. Barth, JR. ,  Kangguo Cheng ,  Michael Sperling ,  Geng Wang

发明人： John E. Barth, JR. ,  Kangguo Cheng ,  Michael Sperling ,  Geng Wang

IPC分类号： H01L27/108

CPC分类号： H01L21/76895 ,  H01L23/485 ,  H01L27/10867 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; a passive transistor laterally spaced from the active transistor, wherein at least a portion of the trench capacitor is interposed between the active and passive transistors; an interlevel dielectric disposed upon the active and passive transistors; and a first conductive contact extending through the interlevel dielectric to the drain junction of the active transistor and the at least a portion of the trench capacitor between the active and passive transistors, wherein the first conductive contact electrically connects the trench capacitor to the drain junction of the active transistor.

摘要翻译： 集成电路包括与形成在半导体衬底中的沟槽电容器横向相邻的有源晶体管，所述有源晶体管包括源极结和漏极结，其中阻挡层沿着所述沟槽电容器的外围设置以隔离所述沟槽电容器; 与有源晶体管横向隔开的无源晶体管，其中所述沟槽电容器的至少一部分插入在所述有源和无源晶体管之间; 布置在有源和无源晶体管上的层间电介质; 以及第一导电接触件，其延伸穿过所述有源晶体管的所述有源晶体管和所述沟槽电容器的所述至少一部分的所述层间电介质的漏极结到所述有源和无源晶体管之间，其中所述第一导电接触将所述沟槽电容器电连接到所述沟道电容器 有源晶体管。

公开(公告)号：US20100032742A1

公开(公告)日：2010-02-11

申请号：US12186780

申请日：2008-08-06

申请人： John E. Barth, JR. ,  Kangguo Cheng ,  Michael Sperling ,  Geng Wang

发明人： John E. Barth, JR. ,  Kangguo Cheng ,  Michael Sperling ,  Geng Wang

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L21/76895 ,  H01L23/485 ,  H01L27/10867 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming an integrated circuit comprises: providing a semiconductor topography comprising an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; forming an interlevel dielectric across the semiconductor topography; concurrently etching (i) a first opening through the interlevel dielectric to the drain junction of the active transistor and the trench capacitor, and (ii) a second opening through the interlevel dielectric to the source junction of the active transistor; and filling the first opening and the second opening with a conductive material to form a strap for electrically connecting the trench capacitor to the drain junction of the active transistor and to also form a contact for electrically connecting the source junction to an overlying level of the integrated circuit.

摘要翻译： 一种形成集成电路的方法包括：提供半导体形貌，其包括与形成在半导体衬底中的沟槽电容器横向相邻的有源晶体管，所述有源晶体管包括源极结和漏极结，其中阻挡层沿着外围设置 用于隔离沟槽电容器的沟槽电容器; 在半导体形貌上形成层间电介质; 同时蚀刻（i）通过层间电介质到有源晶体管和沟槽电容器的漏极结的第一开口，以及（ii）通过层间电介质到有源晶体管的源极结的第二开口; 以及用导电材料填充第一开口和第二开口以形成用于将沟槽电容器电连接到有源晶体管的漏极结的带，并且还形成用于将源极结连接到集成的上覆层 电路。

公开(公告)号：US08937345B2

公开(公告)日：2015-01-20

申请号：US13454635

申请日：2012-04-24

申请人： John E. Barth, Jr. ,  Kangguo Cheng ,  Michael Sperling ,  Geng Wang

发明人： John E. Barth, Jr. ,  Kangguo Cheng ,  Michael Sperling ,  Geng Wang

IPC分类号： H01L27/108 ,  H01L21/768 ,  H01L23/485

CPC分类号： H01L21/76895 ,  H01L23/485 ,  H01L27/10867 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; a passive transistor laterally spaced from the active transistor, wherein at least a portion of the trench capacitor is interposed between the active and passive transistors; an interlevel dielectric disposed upon the active and passive transistors; and a first conductive contact extending through the interlevel dielectric to the drain junction of the active transistor and the at least a portion of the trench capacitor between the active and passive transistors, wherein the first conductive contact electrically connects the trench capacitor to the drain junction of the active transistor.

摘要翻译： 集成电路包括与形成在半导体衬底中的沟槽电容器横向相邻的有源晶体管，所述有源晶体管包括源极结和漏极结，其中阻挡层沿着所述沟槽电容器的外围设置以隔离所述沟槽电容器; 与有源晶体管横向隔开的无源晶体管，其中所述沟槽电容器的至少一部分插入在所述有源和无源晶体管之间; 布置在有源和无源晶体管上的层间电介质; 以及第一导电接触件，其延伸穿过所述有源晶体管的所述有源晶体管和所述沟槽电容器的所述至少一部分的所述层间电介质的漏极结到所述有源和无源晶体管之间，其中所述第一导电接触将所述沟槽电容器电连接到所述沟道电容器 有源晶体管。

公开(公告)号：US08227310B2

公开(公告)日：2012-07-24

申请号：US12186780

申请日：2008-08-06

申请人： John E. Barth, Jr. ,  Kangguo Cheng ,  Michael Sperling ,  Geng Wang

发明人： John E. Barth, Jr. ,  Kangguo Cheng ,  Michael Sperling ,  Geng Wang

IPC分类号： H01L21/8242

CPC分类号： H01L21/76895 ,  H01L23/485 ,  H01L27/10867 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming an integrated circuit comprises: providing a semiconductor topography comprising an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; forming an interlevel dielectric across the semiconductor topography; concurrently etching (i) a first opening through the interlevel dielectric to the drain junction of the active transistor and the trench capacitor, and (ii) a second opening through the interlevel dielectric to the source junction of the active transistor; and filling the first opening and the second opening with a conductive material to form a strap for electrically connecting the trench capacitor to the drain junction of the active transistor and to also form a contact for electrically connecting the source junction to an overlying level of the integrated circuit.

摘要翻译： 一种形成集成电路的方法包括：提供半导体形貌，其包括与形成在半导体衬底中的沟槽电容器横向相邻的有源晶体管，所述有源晶体管包括源极结和漏极结，其中阻挡层沿着外围设置 用于隔离沟槽电容器的沟槽电容器; 在半导体形貌上形成层间电介质; 同时蚀刻（i）通过层间电介质到有源晶体管和沟槽电容器的漏极结的第一开口，以及（ii）通过层间电介质到有源晶体管的源极结的第二开口; 以及用导电材料填充第一开口和第二开口以形成用于将沟槽电容器电连接到有源晶体管的漏极结的带，并且还形成用于将源极结连接到集成的上覆层 电路。

公开(公告)号：US08691697B2

公开(公告)日：2014-04-08

申请号：US12943956

申请日：2010-11-11

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L21/302 ,  B44C1/22

CPC分类号： H01L21/31056 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

摘要： A method includes forming patterned lines on a substrate having a predetermined pitch. The method further includes forming spacer sidewalls on sidewalls of the patterned lines. The method further includes forming material in a space between the spacer sidewalls of adjacent patterned lines. The method further includes forming another patterned line from the material by protecting the material in the space between the spacer sidewalls of adjacent patterned lines while removing the spacer sidewalls. The method further includes transferring a pattern of the patterned lines and the another patterned line to the substrate.

摘要翻译： 一种方法包括在具有预定间距的基底上形成图案线。 该方法还包括在图案化线的侧壁上形成间隔壁。 该方法还包括在相邻图案线的间隔壁侧壁之间的空间中形成材料。 该方法还包括通过在相邻图案化线的间隔壁侧壁之间的空间中保护材料同时去除间隔壁侧壁而从该材料形成另一图案化线。 该方法还包括将图案化线和另一图案化线的图案转移到衬底。

公开(公告)号：US08575670B2

公开(公告)日：2013-11-05

申请号：US13316056

申请日：2011-12-09

申请人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L27/108

CPC分类号： H01L27/1203 ,  H01L27/10861 ,  H01L28/91 ,  H01L29/945

摘要： A memory device including an SOI substrate with a buried dielectric layer having a thickness of less than 30 nm, and a trench extending through an SOI layer and the buried dielectric layer into the base semiconductor layer of the SOI substrate. A capacitor is present in a lower portion of the trench. A dielectric spacer is present on the sidewalls of an upper portion of the trench. The dielectric spacer is present on the portions of the trench where the sidewalls are provided by the SOI layer and the buried dielectric layer. A conductive material fill is present in the upper portion of the trench. A semiconductor device is present on the SOI layer that is adjacent to the trench. The semiconductor device is in electrical communication with the capacitor through the conductive material fill.

摘要翻译： 一种存储器件，包括具有厚度小于30nm的掩埋介电层的SOI衬底，以及穿过SOI层的延伸沟槽和埋入电介质层到SOI衬底的基底半导体层中的沟槽。 电容器存在于沟槽的下部。 电介质垫片存在于沟槽上部的侧壁上。 介质间隔物存在于沟槽的部分，其中侧壁由SOI层和埋入的介电层提供。 导电材料填充物存在于沟槽的上部。 半导体器件存在于与沟槽相邻的SOI层上。 半导体器件通过导电材料填充与电容器电连通。

公开(公告)号：US08242549B2

公开(公告)日：2012-08-14

申请号：US12700807

申请日：2010-02-05

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Chengwen Pei ,  Geng Wang

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Chengwen Pei ,  Geng Wang

IPC分类号： H01L27/108

CPC分类号： H01L28/91 ,  H01L21/823431 ,  H01L27/10823 ,  H01L27/1085 ,  H01L27/10876 ,  H01L27/10879 ,  H01L28/60 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor fin having a doping of the first conductivity type and a semiconductor column are formed on a substrate. The semiconductor column and an adjoined end portion of the semiconductor fin are doped with dopants of a second conductivity type, which is the opposite of the first conductivity type. The doped semiconductor column constitutes an inner electrode of a capacitor. A dielectric layer and a conductive material layer are formed on the semiconductor fin and the semiconductor column. The conductive material layer is patterned to form an outer electrode for the capacitor and a gate electrode. A single-sided halo implantation may be performed. Source and drain regions are formed in the semiconductor fin to form an access transistor. The source region is electrically connected to the inner electrode of the capacitor. The access transistor and the capacitor collectively constitute a DRAM cell.

摘要翻译： 在衬底上形成具有第一导电类型掺杂的半导体鳍和半导体柱。 所述半导体柱和所述半导体鳍片的邻接端部掺杂有与所述第一导电类型相反的第二导电类型的掺杂剂。 掺杂半导体柱构成电容器的内部电极。 在半导体鳍片和半导体柱上形成介电层和导电材料层。 图案化导电材料层以形成用于电容器的外部电极和栅电极。 可以进行单侧晕圈植入。 源极和漏极区域形成在半导体鳍片中以形成存取晶体管。 源极区域电连接到电容器的内部电极。 存取晶体管和电容器共同构成DRAM单元。

公开(公告)号：US20100283093A1

公开(公告)日：2010-11-11

申请号：US12437242

申请日：2009-05-07

申请人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

发明人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

IPC分类号： H01L27/10 ,  H01L21/02

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10861 ,  H01L29/945

摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.

摘要翻译： 提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和 内电极 以及位于沟槽电容器上方的半导体器件。 半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。 存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。