公开(公告)号：US5926738A

公开(公告)日：1999-07-20

申请号：US104074

申请日：1998-06-24

申请人： John E. Cronin ,  Thomas J. Hartswick ,  Anthony K. Stamper

发明人： John E. Cronin ,  Thomas J. Hartswick ,  Anthony K. Stamper

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L21/76838 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S257/903

摘要： The preferred embodiment of the present invention provides increased conductivity between interlevel interconnection lines. The preferred embodiment uses sidewall spacers on the sides of the interconnection lines to increase the contact area between interconnection lines and interconnect studs. This increase in area improves connection resistance and allows further device scaling without unacceptable decreases in the conductivity of the connection, and without adding significant expense in the fabrication process.

摘要翻译： 本发明的优选实施例提供了层间互连线之间增加的电导率。 优选实施例在互连线的侧面上使用侧壁间隔件以增加互连线和互连柱之间的接触面积。 面积的这种增加提高了连接电阻，并且允许进一步的器件定标，而不会导致连接的电导率的不可接受的降低，并且在制造过程中不增加显着的费用。

公开(公告)号：US5808364A

公开(公告)日：1998-09-15

申请号：US838371

申请日：1997-04-08

申请人： John E. Cronin ,  Thomas J. Hartswick ,  Anthony K. Stamper

发明人： John E. Cronin ,  Thomas J. Hartswick ,  Anthony K. Stamper

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L27/01 ,  H01L29/40

CPC分类号： H01L21/76838 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S257/903

摘要： The preferred embodiment of the present invention provides increased conductivity between interlevel interconnection lines. The preferred embodiment uses sidewall spacers on the sides of the interconnection lines to increase the contact area between interconnection lines and interconnect studs. This increase in area improves connection resistance and allows further device scaling without unacceptable decreases in the conductivity of the connection, and without adding significant expense in the fabrication process.

摘要翻译： 本发明的优选实施例提供了层间互连线之间增加的电导率。 优选实施例在互连线的侧面上使用侧壁间隔件以增加互连线和互连柱之间的接触面积。 面积的这种增加提高了连接电阻，并且允许进一步的器件缩放，而不会导致连接的导电性的不可接受的降低，并且不会在制造过程中增加显着的费用。

公开(公告)号：US5907763A

公开(公告)日：1999-05-25

申请号：US702082

申请日：1996-08-23

申请人： Anthony K. Stamper ,  Thomas J. Hartswick

发明人： Anthony K. Stamper ,  Thomas J. Hartswick

IPC分类号： H01L23/544 ,  H01L21/66

CPC分类号： H01L22/34 ,  H01L2924/0002

摘要： A method and device to monitor integrated temperature in a heat cycle process is disclosed. A monitor wafer, according to one embodiment, comprises a substrate, typically a silicon wafer, having films of two conductive materials of selected electrical resistances, sequentially deposited thereon. Suitable conductive materials react with each other in the presence of heat to yield a layer of a third, non-conductive or less conductive, material at the interface of the two conductive materials. The thickness of each of the films of the two conductive materials is selected such that the entire thickness is not consumed in the formation of the layer of a third material. Following the heat exposure, electrical resistance of the monitor wafer is determined and compared with the monitor wafer's selected pre-heat electrical resistance. The change in electrical resistance is then correlated to temperature by a thermocouple probe on a set of test wafers having the same blanket metal structure as the monitor wafer.

摘要翻译： 公开了一种在热循环过程中监测集成温度的方法和装置。 根据一个实施例，监视器晶片包括通常为硅晶片的衬底，其具有顺序地沉积在其上的选定电阻的两个导电材料的膜。 合适的导电材料在热的存在下彼此反应，以在两个导电材料的界面处产生第三，非导电或更少导电材料的层。 选择两种导电材料的每个膜的厚度，使得在形成第三材料层时整个厚度不消耗。 在曝光之后，确定监视晶片的电阻并将其与监视晶片所选择的预热电阻进行比较。 然后通过热电偶探针将电阻变化与具有与监视晶片相同的毯子金属结构的一组测试晶片相关。

公开(公告)号：US5523253A

公开(公告)日：1996-06-04

申请号：US389529

申请日：1995-02-16

申请人： Richard A. Gilmour ,  Thomas J. Hartswick ,  David C. Thomas ,  Ronald R. Uttecht ,  Erick G. Walton

发明人： Richard A. Gilmour ,  Thomas J. Hartswick ,  David C. Thomas ,  Ronald R. Uttecht ,  Erick G. Walton

IPC分类号： H01L23/62 ,  H01L21/82

CPC分类号： H01L23/62 ,  H01L2924/0002

摘要： The present disclosure sets forth an improved integrated circuit in which circuit elements, adjacent to a fuse, are protected by barriers positioned adjacent the fuse. In the improved integrated circuit the barriers are non-frangible, high melting point structures buried in the passivating layer, covering a wiring layer containing a fuse, and are between the fuse and adjacent circuit elements in the wiring layer structures.Also taught is a method of protecting circuit elements adjacent a fuse comprising the steps of depositing an insulating layer on the surface of a semiconductor device having active regions therein, forming a plurality of fuses and circuit elements in said layer, coating said fuses and elements with a second insulating layer, patterning said second insulating layer to form grooves between each of said fuses and any adjacent fuse or circuit element, and depositing a high melting point and non-frangible material in said grooves.

摘要翻译： 本公开提出了一种改进的集成电路，其中与保险丝相邻的电路元件由位于保险丝附近的屏障保护。 在改进的集成电路中，阻挡层是非易碎的，高熔点结构掩埋在钝化层中，覆盖包含保险丝的布线层，并且位于布线层结构中的熔丝和相邻的电路元件之间。 还教导了一种保护靠近熔丝的电路元件的方法，包括以下步骤：在其中具有有源区的半导体器件的表面上沉积绝缘层，在所述层中形成多个保险丝和电路元件，将所述保险丝和元件涂覆 第二绝缘层，图案化所述第二绝缘层以在每个所述保险丝和任何相邻的熔丝或电路元件之间形成槽，以及在所述槽中沉积高熔点和非易碎材料。

公开(公告)号：US06627926B2

公开(公告)日：2003-09-30

申请号：US09788631

申请日：2001-02-16

申请人： Thomas J. Hartswick ,  Mark E. Masters

发明人： Thomas J. Hartswick ,  Mark E. Masters

IPC分类号： H01L2710

CPC分类号： H01L22/32 ,  H01L23/522 ,  H01L2924/0002 ,  Y10S438/926 ,  H01L2924/00

摘要： In a semiconductor device using fill shape patterns incorporated into wiring levels to increase the planarity of the wiring levels, the fill shapes are aligned from one wiring level to another wiring level to provide lines of sight to lower wiring levels for visual inspection. Also, in accordance with the invention, selected aligned fill shapes are interconnected with vias to form conductive stacks for contacting lower wiring level conductive wires from upper wiring levels in order to perform electrical test probing/diagnostics.

摘要翻译： 在使用并入布线层的填充形状图形以增加布线层的平面度的半导体器件中，填充形状从一个布线级别对准到另一布线级别，以提供用于目视检查的较低布线级别的视线。 此外，根据本发明，选定的对齐填充形状与通孔互连以形成导电叠层，用于接触来自上布线层的下布线层导电线，以便进行电测试探测/诊断。

公开(公告)号：US5034348A

公开(公告)日：1991-07-23

申请号：US567992

申请日：1990-08-16

申请人： Thomas J. Hartswick ,  Carter W. Kaanta ,  Pei-Ing P. Lee ,  Terrance M. Wright

发明人： Thomas J. Hartswick ,  Carter W. Kaanta ,  Pei-Ing P. Lee ,  Terrance M. Wright

IPC分类号： H01L21/027 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/8234 ,  H01L23/52 ,  H01L27/06 ,  H01L29/78

CPC分类号： H01L29/66575 ,  H01L21/0276 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/28518

摘要： A method for forming reactive metal silicide layers at two spaced locations on a silicon substrate, which layers can be of different thicknesses and/or of different reactive metals is provided. A sililcon substrate has a silicon dioxide layer formed thereon followed by the formation of a polysilicon layer on the silicon dioxide layer, followed by forming a layer of refractory metal, e.g. titanium on the polysilicon. A non-reflecting material, e.g. titanium nitride is formed on the refractory metal. Conventional photoresist techniques are used to pattern the titanium nitride, the titanium and polysilicon, and the titanium is reacted with the contacted polysilicon to form a titanium silicide. The portion of silicon dioxide overlying the silicon substrate is then removed and the exposed substrate is ion implanted to form source/drain regions. A second layer of refractory metal, either titanium or some other refractory metal, is deposited over the source/drain region, and either over the titanium nitride, or over the first formed silicide by first removing the titanium nitride. The second layer of refractory metal is reacted with the substrate at the source/drain region to form a refractory metal silicide, after which the unreacted refractory metal is removed.

公开(公告)号：US06274393B1

公开(公告)日：2001-08-14

申请号：US09062967

申请日：1998-04-20

申请人： Thomas J. Hartswick

发明人： Thomas J. Hartswick

IPC分类号： H01L2166

CPC分类号： H01L22/12 ,  Y10S438/975

摘要： A method for determining the quality of features of a photoresist pattern, especially for vias and contacts, formed on a semiconductor wafer. A photoresist mask layer having a pattern of openings therein is deposited onto the wafer, and a test region (kerf) of the wafer is marked through the openings in the mask layer. In a preferred embodiment, the mask layer is a photoresist layer, although in alternative embodiments the mask layer could be provided as an insulator mask layer or a metal mask layer. The marking transfers an image of the bottom of the mask layer into the substrate by etching, such as by rastering a focused ion beam over the openings in the mask layer in the presence of an etchant gas. This provides an etched mark in the wafer defined by the passage of the focused ion beam through the mask opening. In alternative embodiments, the marking could be performed by staining or dyeing. Following the marking step, the mask layer is removed from the test region to facilitate an inspection of the wafer for the presence of the marking while leaving the mask layer in place over remaining portions of the wafer.

摘要翻译： 一种用于确定在半导体晶片上形成的光致抗蚀剂图案的特征质量，特别是用于通孔和触点的质量的方法。 将具有其中的开口图案的光致抗蚀剂掩模层沉积在晶片上，并且通过掩模层中的开口标记晶片的测试区域（切口）。 在优选实施例中，掩模层是光致抗蚀剂层，尽管在替代实施例中，掩模层可以被提供为绝缘体掩模层或金属掩模层。 标记通过蚀刻将掩模层底部的图像转移到衬底中，例如通过在存在蚀刻剂气体的情况下将聚焦离子束掠过掩模层中的开口。 这在晶片中通过聚焦离子束通过掩模开口的通道所限定的蚀刻标记。 在替代实施例中，标记可以通过染色或染色进行。 在标记步骤之后，将掩模层从测试区域移除，以便于在晶片的剩余部分离开掩模层的同时检查晶片是否存在标记。

公开(公告)号：US06251773B1

公开(公告)日：2001-06-26

申请号：US09473635

申请日：1999-12-28

申请人： Thomas J. Hartswick ,  Mark E. Masters

发明人： Thomas J. Hartswick ,  Mark E. Masters

IPC分类号： H01L214763

CPC分类号： H01L22/32 ,  H01L23/522 ,  H01L2924/0002 ,  Y10S438/926 ,  H01L2924/00

摘要： In a semiconductor device using fill shape patterns incorporated into wiring levels to increase the planarity of the wiring levels, the fill shapes are aligned from one wiring level to another wiring level to provide lines of sight to lower wiring levels for visual inspection. Also, in accordance with the invention, selected aligned fill shapes are interconnected with vias to form conductive stacks for contacting lower wiring level conductive wires from upper wiring levels in order to perform electrical test probing/diagnostics.

摘要翻译： 在使用并入布线层的填充形状图形以增加布线层的平面度的半导体器件中，填充形状从一个布线级别对准到另一布线级别，以提供用于目视检查的较低布线级别的视线。 此外，根据本发明，选定的对齐填充形状与通孔互连以形成导电叠层，用于接触来自上布线层的下布线层导电线，以便进行电测试探测/诊断。

公开(公告)号：US5420455A

公开(公告)日：1995-05-30

申请号：US221715

申请日：1994-03-31

申请人： Richard A. Gilmour ,  Thomas J. Hartswick ,  David C. Thomas ,  Ronald R. Uttecht ,  Erick G. Walton

发明人： Richard A. Gilmour ,  Thomas J. Hartswick ,  David C. Thomas ,  Ronald R. Uttecht ,  Erick G. Walton

IPC分类号： H01L23/62 ,  H01L27/02

CPC分类号： H01L23/62 ,  H01L2924/0002

摘要： The present disclosure sets forth an improved integrated circuit in which circuit elements, adjacent to a fuse, are protected by barriers positioned adjacent the fuse. In the improved integrated circuit the barriers are non-frangible, high melting point structures buried in the passivating layer, covering a wiring layer containing a fuse, and are between the fuse and adjacent circuit elements in the wiring layer structures.Also taught is a method of protecting circuit elements adjacent a fuse comprising the steps of depositing an insulating layer on the surface of a semiconductor device having active regions therein, forming a plurality of fuses and circuit elements in said layer, coating said fuses and elements with a second insulating layer, patterning said second insulating layer to form grooves between each of said fuses and any adjacent fuse or circuit element, and depositing a high melting point and non-frangible material in said grooves.

摘要翻译： 本公开提出了一种改进的集成电路，其中与保险丝相邻的电路元件由位于保险丝附近的屏障保护。 在改进的集成电路中，阻挡层是非易碎的，高熔点结构掩埋在钝化层中，覆盖包含保险丝的布线层，并且位于布线层结构中的熔丝和相邻的电路元件之间。 还教导了一种保护靠近熔丝的电路元件的方法，包括以下步骤：在其中具有有源区的半导体器件的表面上沉积绝缘层，在所述层中形成多个保险丝和电路元件，将所述保险丝和元件涂覆 第二绝缘层，图案化所述第二绝缘层以在每个所述保险丝和任何相邻的熔丝或电路元件之间形成槽，以及在所述槽中沉积高熔点和非易碎材料。