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26 条记录 (耗时 0.014 秒)

    Fusible links with improved interconnect structure
    3.
    发明授权
    Fusible links with improved interconnect structure 失效
    具有改进的互连结构的易熔链

    公开(公告)号：US5760674A

    公开(公告)日：1998-06-02

    申请号：US563691

    申请日：1995-11-28

    申请人： Richard A. Gilmour ,  Ronald R. Uttecht ,  Erick G. Walton

    发明人： Richard A. Gilmour ,  Ronald R. Uttecht ,  Erick G. Walton

    IPC分类号： H01L23/525 ,  H01H85/00

    CPC分类号： H01L23/5258 ,  H01L2924/0002

    摘要： The fuse link includes a first and second interconnect, with interconnects each being substantially longer than deep. The interconnects are disposed toward each other with a insulator region between them. A fusible conductor, spanning the insulator region, is attached at the top of the interconnects. The present device allows the length of the fusible conductor to be shortened, and results in a fuse link that can be consistently blown with a single laser pulse. Additionally, the fuse link can be used in a staggered layout. The staggered layout of parallel fuse links allows a high number of links in a relatively small area, with or without the use of tungsten barriers, and allows accessing all fuse links through a single fuse blow window.

    摘要翻译： 熔丝连接件包括第一和第二互连件，其互连件基本上比深度长。 互连通过它们之间的绝缘体区域彼此相对设置。 跨越绝缘体区域的可熔导体连接在互连的顶部。 本装置允许可熔导体的长度缩短，并且导致可以用单个激光脉冲一致地熔断的熔丝链。 此外，熔丝链可以以交错的布局使用。 平行熔丝链的交错布局允许在有或没有使用钨屏障的情况下，在相对较小的区域中有大量的连接，并且允许通过单个保险丝熔断窗口访问所有熔丝链。

    Array fuse damage protection devices and fabrication method
    6.
    发明授权
    Array fuse damage protection devices and fabrication method 失效
    阵列保险丝损坏保护装置及制造方法

    公开(公告)号：US5420455A

    公开(公告)日：1995-05-30

    申请号：US221715

    申请日：1994-03-31

    申请人： Richard A. Gilmour ,  Thomas J. Hartswick ,  David C. Thomas ,  Ronald R. Uttecht ,  Erick G. Walton

    发明人： Richard A. Gilmour ,  Thomas J. Hartswick ,  David C. Thomas ,  Ronald R. Uttecht ,  Erick G. Walton

    IPC分类号： H01L23/62 ,  H01L27/02

    CPC分类号： H01L23/62 ,  H01L2924/0002

    摘要： The present disclosure sets forth an improved integrated circuit in which circuit elements, adjacent to a fuse, are protected by barriers positioned adjacent the fuse. In the improved integrated circuit the barriers are non-frangible, high melting point structures buried in the passivating layer, covering a wiring layer containing a fuse, and are between the fuse and adjacent circuit elements in the wiring layer structures.Also taught is a method of protecting circuit elements adjacent a fuse comprising the steps of depositing an insulating layer on the surface of a semiconductor device having active regions therein, forming a plurality of fuses and circuit elements in said layer, coating said fuses and elements with a second insulating layer, patterning said second insulating layer to form grooves between each of said fuses and any adjacent fuse or circuit element, and depositing a high melting point and non-frangible material in said grooves.

    摘要翻译： 本公开提出了一种改进的集成电路，其中与保险丝相邻的电路元件由位于保险丝附近的屏障保护。 在改进的集成电路中，阻挡层是非易碎的，高熔点结构掩埋在钝化层中，覆盖包含保险丝的布线层，并且位于布线层结构中的熔丝和相邻的电路元件之间。 还教导了一种保护靠近熔丝的电路元件的方法，包括以下步骤：在其中具有有源区的半导体器件的表面上沉积绝缘层，在所述层中形成多个保险丝和电路元件，将所述保险丝和元件涂覆 第二绝缘层，图案化所述第二绝缘层以在每个所述保险丝和任何相邻的熔丝或电路元件之间形成槽，以及在所述槽中沉积高熔点和非易碎材料。

    Method for manufacturing self-compensating resistors within an integrated circuit
    8.
    发明授权
    Method for manufacturing self-compensating resistors within an integrated circuit 有权
    在集成电路内制造自补偿电阻的方法

    公开(公告)号：US07052925B2

    公开(公告)日：2006-05-30

    申请号：US10709039

    申请日：2004-04-08

    申请人： William J. Murphy ,  Edmund J. Sprogis ,  Anthony K. Stamper ,  Erick G. Walton

    发明人： William J. Murphy ,  Edmund J. Sprogis ,  Anthony K. Stamper ,  Erick G. Walton

    IPC分类号： H01L31/26

    CPC分类号： H01L28/20 ,  H01L27/0802 ,  Y10T29/49082 ,  Y10T29/49085

    摘要： A method for manufacturing a self-compensating resistor within an integrated circuit is disclosed. The self-compensating resistor includes a first resistor and a second resistor. The first resistor having a first resistance value is initially formed, and then the second resistor having a second resistance value is subsequently formed. The second resistor is connected in series with the first resistor. The second resistance value is less than the first resistance value, but the total resistance value of the first and second resistors lies beyond a desired target resistance range. Finally, an electric current is sent to the second resistor to change the dimension of the second resistor such that the total resistance value of the first and second resistors falls within the desired target resistance range.

    摘要翻译： 公开了一种在集成电路内制造自补偿电阻器的方法。 自补偿电阻器包括第一电阻器和第二电阻器。 初始形成具有第一电阻值的第一电阻器，然后形成具有第二电阻值的第二电阻器。 第二个电阻与第一个电阻串联。 第二电阻值小于第一电阻值，但是第一和第二电阻器的总电阻值超过期望的目标电阻范围。 最后，向第二电阻器发送电流以改变第二电阻器的尺寸，使得第一和第二电阻器的总电阻值落在期望的目标电阻范围内。

    Fusible links formed on interconnects which are at least twice as long as they are deep
    9.
    发明授权
    Fusible links formed on interconnects which are at least twice as long as they are deep 失效
    在互连上形成的可熔链，至少是深度的两倍

    公开(公告)号：US6054339A

    公开(公告)日：2000-04-25

    申请号：US810587

    申请日：1997-03-04

    申请人： Richard A. Gilmour ,  Ronald R. Uttecht ,  Erick G. Walton

    发明人： Richard A. Gilmour ,  Ronald R. Uttecht ,  Erick G. Walton

    IPC分类号： H01L23/525 ,  H01L21/82

    CPC分类号： H01L23/5258 ,  H01L2924/0002

    摘要： A shortened fuse link is disclosed. The fuse link comprises a first and second interconnect, with interconnects each being substantially longer than deep. The interconnects are disposed toward each other with a insulator region between them. A fusible conductor, spanning the insulator region, is attached at the top of the interconnects. The present device allows the length of the fusible conductor to be shortened, and results in a fuse link that can be consistently blown with a single laser pulse. Additionally, the fuse link can be used in a staggered layout. The staggered layout of parallel fuse links allows a high number of links in a relatively small area, with or without the use of tungsten barriers, and allows accessing all fuse links through a single fuse blow window.

    摘要翻译： 公开了一种缩短的熔断体。 熔丝连接件包括第一和第二互连件，每个互连件基本上比深度长。 互连通过它们之间的绝缘体区域彼此相对设置。 跨越绝缘体区域的可熔导体连接在互连的顶部。 本装置允许可熔导体的长度缩短，并且导致可以用单个激光脉冲一致地熔断的熔丝链。 此外，熔丝链可以以交错的布局使用。 平行熔丝链的交错布局允许在有或没有使用钨屏障的情况下，在相对较小的区域中有大量的连接，并且允许通过单个保险丝熔断窗口访问所有熔丝链。

    Slurry injection technique for chemical-mechanical polishing
    10.
    发明授权
    Slurry injection technique for chemical-mechanical polishing 失效
    用于化学机械抛光的浆料注射技术

    公开(公告)号：US5997392A

    公开(公告)日：1999-12-07

    申请号：US898063

    申请日：1997-07-22

    申请人： Timothy S. Chamberlin ,  Matthew K. Miller ,  Erick G. Walton

    发明人： Timothy S. Chamberlin ,  Matthew K. Miller ,  Erick G. Walton

    IPC分类号： B24B37/04 ,  B24B57/02 ,  H01L21/304 ,  B24B57/00

    CPC分类号： B24B37/04 ,  B24B57/02

    摘要： An apparatus for polishing a semiconductor wafer is provided comprising a wafer carrier to provide a force against a wafer and a rotating polishing pad during the polishing operation and a polishing slurry distributor device disposed to provide a spray of the slurry on the polishing pad. The wafer is polished using less slurry than a conventional polishing apparatus while still maintaining the polishing rates and polishing uniformity of the prior art polishing apparatus. A preferred spraying means is a closed elongated tube having a plurality of openings which tube is positioned over at least one-half the diameter of the polishing pad and a polishing slurry under pressure is directed onto the surface of the pad, preferably in a substantially transverse spray stream.

    摘要翻译： 提供了一种用于抛光半导体晶片的装置，其包括晶片载体，以在抛光操作期间提供抵抗晶片和旋转抛光垫的力，以及抛光浆料分配器装置，其设置成在抛光垫上提供浆料喷射。 使用比常规抛光装置更少的浆料抛光晶片，同时仍保持现有技术抛光装置的抛光速率和抛光均匀性。 优选的喷射装置是具有多个开口的封闭细长管，其中管被定位在抛光垫的直径的至少二分之一上，并且在压力下的抛光浆液被引导到垫的表面上，优选地基本上横向 喷雾流。