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公开(公告)号：US5926738A
公开(公告)日：1999-07-20
申请号：US104074
申请日：1998-06-24
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L23/48
CPC分类号： H01L21/76838 , H01L21/76886 , H01L23/5226 , H01L23/53223 , H01L2924/0002 , Y10S257/903
摘要： The preferred embodiment of the present invention provides increased conductivity between interlevel interconnection lines. The preferred embodiment uses sidewall spacers on the sides of the interconnection lines to increase the contact area between interconnection lines and interconnect studs. This increase in area improves connection resistance and allows further device scaling without unacceptable decreases in the conductivity of the connection, and without adding significant expense in the fabrication process.
摘要翻译： 本发明的优选实施例提供了层间互连线之间增加的电导率。 优选实施例在互连线的侧面上使用侧壁间隔件以增加互连线和互连柱之间的接触面积。 面积的这种增加提高了连接电阻，并且允许进一步的器件定标，而不会导致连接的电导率的不可接受的降低，并且在制造过程中不增加显着的费用。
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公开(公告)号：US5808364A
公开(公告)日：1998-09-15
申请号：US838371
申请日：1997-04-08
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L23/48 , H01L23/52 , H01L27/01 , H01L29/40
CPC分类号： H01L21/76838 , H01L21/76886 , H01L23/5226 , H01L23/53223 , H01L2924/0002 , Y10S257/903
摘要： The preferred embodiment of the present invention provides increased conductivity between interlevel interconnection lines. The preferred embodiment uses sidewall spacers on the sides of the interconnection lines to increase the contact area between interconnection lines and interconnect studs. This increase in area improves connection resistance and allows further device scaling without unacceptable decreases in the conductivity of the connection, and without adding significant expense in the fabrication process.
摘要翻译： 本发明的优选实施例提供了层间互连线之间增加的电导率。 优选实施例在互连线的侧面上使用侧壁间隔件以增加互连线和互连柱之间的接触面积。 面积的这种增加提高了连接电阻，并且允许进一步的器件缩放，而不会导致连接的导电性的不可接受的降低，并且不会在制造过程中增加显着的费用。
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公开(公告)号：US06213376B1
公开(公告)日：2001-04-10
申请号：US09098828
申请日：1998-06-17
IPC分类号： B23K3704
CPC分类号： H01L21/6835 , B23K37/0408 , B23K2101/40 , H01L25/50 , H01L2221/68313 , H01L2224/05568 , H01L2224/05573 , H01L2224/056 , H01L2224/16 , H01L2924/30105 , Y10T29/53978 , H01L2924/00014
摘要： An apparatus used for holding a first semiconductor device in proper alignment to a second semiconductor device, whose size is different from the first device, while performing a C4 bond between the two devices. The apparatus for holding the two devices in proper alignment consists of a holding fixture, which includes upper and lower pocket receptacles for receiving the semiconductor devices. The semiconductor devices are placed into the respective upper and lower slots aligned to two or more edges of the holding fixture.
摘要翻译： 一种用于在与两个装置之间执行C4键的同时保持尺寸与第一装置不同的第二半导体装置正确对准的装置。 用于将两个装置保持正确对准的装置包括保持夹具，其包括用于接收半导体装置的上部和下部口袋容器。 将半导体器件放置在与保持夹具的两个或更多个边缘对准的相应的上部和下部狭缝中。
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4.发明授权Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging 失效将薄层连接到单片电子模块表面的方法和工件以及相关的模块封装
公开(公告)号：US5567654A
公开(公告)日：1996-10-22
申请号：US313976
申请日：1994-09-28
申请人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , John E. Cronin , Wayne J. Howell , James M. Leas , David J. Perlman
发明人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , John E. Cronin , Wayne J. Howell , James M. Leas , David J. Perlman
IPC分类号： H01L21/98 , H01L23/498 , H01L25/065 , H01L25/18 , H01L21/60
CPC分类号： H01L25/50 , H01L23/49827 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/16145 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/49107 , H01L2224/49109 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06582 , H01L2225/06586 , H01L2225/06589 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01039 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/15312 , H01L2924/1532 , H01L2924/16152 , H01L2924/16195 , H01L2924/30107
摘要： A fabrication method and resultant monolithic electronic module having a separately formed thin-film layer attached to a side surface. The fabrication method includes providing an electronic module composed of stacked integrated circuit chips. A thin-film layer is separately formed on a temporary support which is used to attach the thin-film layer to the electronic module. The disclosed techniques may also be used for attaching an interposer, which may include active circuity, to an electronic module. Specific details of the fabrication method, resulting multichip packages, and various thin-film structures are set forth.
摘要翻译： 一种具有附接到侧表面的单独形成的薄膜层的制造方法和所得到的单片电子模块。 该制造方法包括提供由堆叠的集成电路芯片组成的电子模块。 在用于将薄膜层附着到电子模块的临时支架上分开形成薄膜层。 所公开的技术还可以用于将可包括有源电路的插入件附接到电子模块。 阐述了制造方法，所得到的多芯片封装以及各种薄膜结构的具体细节。
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5.发明授权Process for forming multi-level coplanar conductor/insulator films employing photosensitive polymide polymer compositions 失效形成多层共晶导体/绝缘膜的方法使用感光聚合物聚合物组合物
公开(公告)号：US5229257A
公开(公告)日：1993-07-20
申请号：US516415
申请日：1990-04-30
申请人： John E. Cronin , Carter W. Kaanta , Pei-Ing P. Lee , Rosemary A. Previti-Kelly , James G. Ryan , Jung H. Yoon
发明人： John E. Cronin , Carter W. Kaanta , Pei-Ing P. Lee , Rosemary A. Previti-Kelly , James G. Ryan , Jung H. Yoon
IPC分类号： C08G73/10 , G03F7/038 , H01L21/312 , H01L21/768 , H01L23/522 , H05K3/00 , H05K3/04 , H05K3/10 , H05K3/46
CPC分类号： H01L21/76828 , H01L21/76807 , H01L21/76814 , H01L21/76825 , H01L23/5226 , H05K3/0023 , H05K3/467 , H01L2924/0002 , H01L2924/12044 , H05K2201/0154 , H05K3/045 , H05K3/107 , H05K3/465
摘要： Disclosed is a process for producing multi-level conductor/insulator films on a processed semiconductor substrate having a conductor pattern. The insulator layers, each comprise a photosensitive polyimide polymer composition, and this allows the desired wiring channels and stud vias to be formed directly in the insulator layers, without the use of separate masking layers and resulting image transfer steps, thus providing a less cumbersome and costly process.
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公开(公告)号：US5194928A
公开(公告)日：1993-03-16
申请号：US842307
申请日：1992-02-26
IPC分类号： C08G73/10 , C09D4/00 , G03F7/075 , G03F7/09 , H01L21/312
CPC分类号： H01L21/3121 , C08G73/106 , C09D4/00 , G03F7/0757 , G03F7/094 , H01L21/312 , Y10S438/958
摘要： Disclosed is a process for passivating a metal surface in a metal/polyimide structure, such as a polyimide layer on a semiconductor substrate containing a pattern of metallization. The process involves the formation of an intermediate layer of a silsesquioxane polymer between the polyimide layer and the substrate. The silsesquioxane layer passivates the metal, to inhibit interaction between the metal surface and the polyimide precursor material used in forming the polyimide, to provide a moisture-resistant and oxidation-resistant interface.
摘要翻译： 公开了一种在包含金属化图案的半导体衬底上的金属/聚酰亚胺结构如聚酰亚胺层中钝化金属表面的方法。 该方法涉及在聚酰亚胺层和基底之间形成倍半硅氧烷聚合物的中间层。 倍半硅氧烷层钝化金属，以抑制金属表面与形成聚酰亚胺所用的聚酰亚胺前体材料之间的相互作用，以提供耐湿和抗氧化的界面。
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公开(公告)号：US5136124A
公开(公告)日：1992-08-04
申请号：US585256
申请日：1990-09-19
IPC分类号： H01L21/3205 , H01L21/48 , H01L21/768 , H05K3/00 , H05K3/06 , H05K3/10 , H05K3/46
CPC分类号： H01L21/76808 , H01L21/32053 , H01L21/4846 , H01L21/76877 , H01L21/7688 , H01L2221/1031 , H01L2221/1036 , H05K3/0017 , H05K3/06 , H05K3/107 , H05K3/4644
摘要： A method for forming an electrically conductive line between two layers of insulating material and method for connecting the line through both layers of the insulating material to the opposite surfaces is provided. In the method, first, second and third layers of insulating material are provided wherein the first and third layers are separated by the second layer of insulating material which is different in etch rate from the first and third layers. The edge portion of all three layers is exposed and the insulating layer of the second material is selectively etched to remove the revealed edge portion and provide a slot between the first and third layers of insulating material. Also openings are provided in both the first and third layers of insulating material which communicate with the slot and extend respectively through the layers of the first and third insulating material. Thereafter, a conductive material such as tungsten is deposited in the slot and the openings and also on the face of the stacked insulating material. Finally, the excess tungsten is removed from the faces of the insulating material of the first and third layers leaving a conductive line sandwiched between the first and third insulating layers of the material; also metal remains in the openings formed to thereby form conductive studs extending from the line to the opposite surfaces of the insulating material sandwich so formed.
摘要翻译： 提供了用于在两层绝缘材料之间形成导电线的方法以及将绝缘材料的两层连接到相对表面的方法。 在该方法中，提供了绝缘材料的第一层，第二层和第三层，其中第一层和第三层由第二层绝缘材料隔开，蚀刻速率与第一层和第三层不同。 暴露所有三层的边缘部分，并且选择性地蚀刻第二材料的绝缘层以去除露出的边缘部分，并在第一和第三绝缘材料层之间提供槽。 在第一和第三绝缘材料层中的开口均设置有与槽连通并分别延伸穿过第一和第三绝缘材料的层。 此后，诸如钨的导电材料沉积在槽和开口中以及堆叠的绝缘材料的表面上。 最后，从第一和第三层的绝缘材料的表面去除多余的钨，留下夹在材料的第一和第三绝缘层之间的导线; 在形成的开口中也保留有金属，从而形成从线形延伸到形成的绝缘材料夹层的相对表面的导电柱。
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公开(公告)号：US6139661A
公开(公告)日：2000-10-31
申请号：US175916
申请日：1998-10-20
CPC分类号： H05K3/321 , C09J5/00 , H05K2201/10689 , H05K2203/0557 , H05K2203/1476 , H05K2203/162 , H05K2203/176 , Y10T29/4913 , Y10T29/49147
摘要： A method for temporarily attaching an electrical component to a pad, testing the component, removing and replacing the component if necessary, and making a final attachment of the component to the pad. The method provides for attachment and removal of components, to and from pads located on the substrate of a printed circuit board, wherein the method enables components to be easily removed prior to final assembly without damaging the circuit board or components mounted thereon. The method utilizes a layer of conductive, radiation-curable adhesive placed between the component's lead and the pad. Radiation is then directed through a mask onto a portion of the adhesive layer, which cures the portion while leaving a remaining area of the adhesive layer uncured. Because the portion of the adhesive layer that receives the radiation, and is consequently cured by the radiation, is only a limited portion of the whole adhesive layer, the component may be easily removed from the pad by applying a small mechanical force. Following such removal, the component or a replacement thereof may be attached to the remaining area. The final stage of the method cures the remaining area of uncured adhesive by exposing the remaining area to radiation.
摘要翻译： 一种用于将电气部件临时附接到焊盘，测试部件，如果需要移除和更换部件的方法，以及将部件最终附接到焊盘。 该方法提供了附接和去除位于印刷电路板的基板上的焊盘的部件，其中该方法使得能够在最终组装之前容易地移除部件，而不会损坏安装在其上的电路板或部件。 该方法利用放置在部件的引线和焊盘之间的导电的可辐射固化的粘合剂层。 然后将辐射通过掩模引导到粘合剂层的一部分上，其固化该部分，同时留下未固化的粘合剂层的剩余区域。 由于接收辐射并因此被辐射固化的粘合剂层的部分仅仅是整个粘合剂层的有限部分，所以通过施加小的机械力可以容易地将该部件从焊盘移除。 在这种移除之后，组件或其替换可以附接到剩余区域。 该方法的最后阶段通过将剩余区域暴露于辐射来固化未固化的粘合剂的剩余面积。
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公开(公告)号：US6037661A
公开(公告)日：2000-03-14
申请号：US771598
申请日：1996-12-20
IPC分类号： H01L23/24 , H01L23/495 , H01L31/0232
CPC分类号： H01L23/49575 , H01L23/24 , H01L2224/05599 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/49171 , H01L2224/85399 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/14
摘要： A semiconductor device which includes a first semiconductor chip mounted on top of a lead frame which is molded within a plastic body. During the molding process a cavity is formed on the bottom of the lead frame. After testing or burn-in of the first chip a second semiconductor chip is mounted and electrically connected to the lead frame. The second chip may then be sealed within the cavity to form a multichip module.
摘要翻译： 一种半导体器件，包括安装在引线框架的顶部上的第一半导体芯片，所述引线框架模制在塑料体内。 在模制过程中，在引线框架的底部形成空腔。 在第一芯片的测试或老化之后，安装第二个半导体芯片并电连接到引线框架。 然后可以将第二芯片密封在空腔内以形成多芯片模块。
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公开(公告)号：US5872025A
公开(公告)日：1999-02-16
申请号：US815452
申请日：1997-03-11
IPC分类号： H01L21/304 , H01L21/301 , H01L21/78 , H01L21/98 , H01L25/065 , H01L21/283 , H01L21/027 , H01L21/18 , H01L21/31
CPC分类号： H01L25/50 , H01L21/78 , H01L25/0657 , H01L2224/24145 , H01L2225/06513 , H01L2225/06541 , H01L2225/06551 , H01L2924/10253 , Y10S148/028 , Y10S438/977
摘要： Stacked three-dimensional devices can be prepared by stacking wafers as an alternative to stacking individual devices. Chip regions are formed on several wafers with each chip region being surrounded by a separation region, such as an insulator filled trench. The wafers are then stacked with the chip regions in alignment. Aligning the wafers can be facilitated using notched regions in the periphery of the wafers. The wafers are then joined together by lamination. After laminating the stacks of wafers, stacks of chips are separated by etching, dicing or other processes, which separate out stacked chip devices from the stacked wafer at the chip separation regions. The process allows several stacked chip devices to be manufactured simultaneously.
摘要翻译： 堆叠的三维器件可以通过堆叠晶片作为堆叠单个器件的替代物来制备。 芯片区域形成在几个晶片上，每个芯片区域被诸如绝缘体填充的沟槽之类的分离区域包围。 然后将晶片与芯片区域对准地堆叠。 可以利用晶片周边的切口区域来调整晶片对准。 然后通过层压将晶片连接在一起。 在堆叠晶片堆叠之后，通过蚀刻，切割或其它工艺来分离芯片堆叠，其在芯片分离区域将堆叠的芯片器件与堆叠晶片分开。 该过程允许同时制造几个堆叠的芯片器件。
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