公开(公告)号：US5597458A

公开(公告)日：1997-01-28

申请号：US500296

申请日：1995-07-10

申请人： John E. Sanchez, Jr. ,  Darin A. Chan ,  Paul R. Besser

发明人： John E. Sanchez, Jr. ,  Darin A. Chan ,  Paul R. Besser

IPC分类号： C23C14/16 ,  C23C14/54 ,  H01L21/768 ,  C23C14/34

CPC分类号： C23C14/541 ,  C23C14/165 ,  H01L21/76838

摘要： A method for forming an alloy film by cooling a substrate during a sputter deposition process. In one embodiment, aluminum-copper (Al-Cu) alloy film is deposited on a substrate while the substrate is maintained at a temperature lower than 100.degree. C. during a sputter deposition process, thereby reducing the precipitation of CuAl.sub.2. The substrate is cooled by pumping a coolant gas through a cooled platen and against the substrate during processing. Subsequent film formation prior to etching is also performed below 100.degree. C. to prevent precipitation of CuAl.sub.2 until the Al-Cu alloy film is etched. Large crystal grains are formed by annealing the substrate after etching.

摘要翻译： 一种通过在溅射沉积工艺期间冷却基板来形成合金膜的方法。 在一个实施例中，在溅射沉积工艺期间，将基板保持在低于100℃的温度下，将铝 - 铜（Al-Cu）合金膜沉积在基板上，由此减少CuAl 2的析出。 通过在处理过程中将冷却剂气体泵送通过冷却的压板并抵靠衬底来冷却衬底。 在蚀刻之前的后续成膜也在低于100℃下进行，以防止CuAl2沉淀，直到蚀刻Al-Cu合金膜。 在蚀刻之后通过退火衬底形成大的晶粒。

公开(公告)号：US07151020B1

公开(公告)日：2006-12-19

申请号：US10839437

申请日：2004-05-04

申请人： Jeffrey P. Patton ,  Austin C. Frenkel ,  Thorsten Kammler ,  Robert J. Chiu ,  Errol Todd Ryan ,  Darin A. Chan ,  Paul R. Besser ,  Paul L. King ,  Minh Van Ngo

发明人： Jeffrey P. Patton ,  Austin C. Frenkel ,  Thorsten Kammler ,  Robert J. Chiu ,  Errol Todd Ryan ,  Darin A. Chan ,  Paul R. Besser ,  Paul L. King ,  Minh Van Ngo

IPC分类号： H01L21/336 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A transition metal layer is formed on the source/drain junctions and on the gate. An interlayer dielectric is formed above the semiconductor substrate. Contacts are then formed in the interlayer dielectric, whereby a silicide is formed from the transition metal layer at a temperature no higher than the maximum temperature at which the interlayer dielectric and the contacts are formed.

摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 在源极/漏极结和栅极上形成过渡金属层。 在半导体衬底上形成层间电介质。 然后在层间电介质中形成触点，由此在不高于形成层间电介质和触点的最高温度的温度下由过渡金属层形成硅化物。

公开(公告)号：US07494885B1

公开(公告)日：2009-02-24

申请号：US10818155

申请日：2004-04-05

申请人： Mario M. Pelella ,  Darin A. Chan ,  Kei-Leong Ho ,  Lu You

发明人： Mario M. Pelella ,  Darin A. Chan ,  Kei-Leong Ho ,  Lu You

IPC分类号： H01L21/00

CPC分类号： H01L29/6659 ,  H01L29/41775 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7833

摘要： According to one exemplary embodiment, a method for forming a field effect transistor on a substrate comprises a step of forming disposable spacers adjacent to a gate stack situated on the substrate, where the disposable spacers comprise amorphous carbon. The disposable spacers can be formed by depositing a layer of amorphous carbon on the gate stack and anisotropically etching the layer of amorphous carbon. The method further comprises forming source and drain regions in the substrate, where the source and drain regions are situated adjacent to the disposable spacers. According to this exemplary embodiment, the method further comprises removing the disposable spacers, where the removal of the disposable spacers causes substantially no gouging in the substrate. The disposable spacers can be removed by using a dry etch process. The method can further comprise forming extension regions in the substrate adjacent to the gate stack prior to forming the disposable spacers.

摘要翻译： 根据一个示例性实施例，用于在衬底上形成场效应晶体管的方法包括形成邻近位于衬底上的栅极堆叠的一次性间隔物的步骤，其中一次性间隔物包括无定形碳。 可以通过在栅极堆叠上沉积无定形碳层并且各向异性地蚀刻无定形碳层来形成一次性间隔物。 该方法还包括在衬底中形成源极和漏极区域，其中源极区域和漏极区域邻近一次性间隔物定位。 根据该示例性实施例，该方法还包括去除一次性间隔件，其中一次性间隔件的移除基本上不引起基板中的气刨。 可以通过使用干法蚀刻工艺去除一次性间隔物。 该方法还可以包括在形成一次性间隔件之前在邻近栅极堆叠的基板中形成延伸区域。

公开(公告)号：US07276755B2

公开(公告)日：2007-10-02

申请号：US11119660

申请日：2005-05-02

申请人： Darin A. Chan

发明人： Darin A. Chan

IPC分类号： H01L29/76

CPC分类号： H01L21/0217 ,  H01L21/02274 ,  H01L21/3145 ,  H01L21/3185 ,  H01L21/76832 ,  H01L21/76895 ,  H01L21/84 ,  H01L27/1203

摘要： An integrated circuit having a plurality of active areas separated from each other by a field region and a method for manufacturing the integrated circuit. A first polysilicon finger is formed over the first active area and the field region and a second polysilicon finger is formed over the second active area and the field region. A first dielectric layer is formed over the first active area and the field region and a second dielectric layer is formed over the second active area and the portion of the first dielectric layer over the field region. A first electrical interconnect is formed over and dielectrically isolated from the first polysilicon finger and a second electrical interconnect is formed over and dielectrically isolated from the second active area. The second electrical interconnect is electrically coupled to the second polysilicon finger.

摘要翻译： 具有通过场区域彼此分离的多个有源区域的集成电路和用于制造集成电路的方法。 在第一有源区域和场区域上形成第一多晶硅指状物，并且在第二有源区域和场区域上形成第二多晶硅指状物。 在第一有源区和场区上形成第一电介质层，并且第二介电层形成在场区上的第二有源区和第一电介质层的部分上。 第一电互连形成在第一多晶硅指状物的上并与之电介质隔离，并且第二电互连形成在第二有源区上并与之相互隔离。 第二电互连电连接到第二多晶硅指状物。

公开(公告)号：US6060393A

公开(公告)日：2000-05-09

申请号：US993888

申请日：1997-12-18

申请人： Minh Van Ngo ,  Darin A. Chan ,  David K. Foote

发明人： Minh Van Ngo ,  Darin A. Chan ,  David K. Foote

IPC分类号： H01L21/768 ,  H01L21/304

CPC分类号： H01L21/76895 ,  H01L21/76801

摘要： A deposition method allows for the forming of a uniform dielectric stop layer that is substantially void of defects caused by outgassing effects. The stop layer is deposited in a reactor chamber at a higher than normal temperature of at least 480.degree. C. The stop layer is then combined with an overlying dielectric layer to provide an inter-level dielectric structure through which a local interconnect can be formed to provide a conductive path to one or more regions of the underlying semiconductor devices.

摘要翻译： 沉积方法允许形成基本上没有由除气效应引起的缺陷的均匀的电介质停止层。 停止层沉积在高于至少480℃的常温的反应器室中。然后将停止层与覆盖的介电层组合以提供层间电介质结构，通过该层间电介质结构可以形成局部互连 为下面的半导体器件的一个或多个区域提供导电路径。

公开(公告)号：US20090193369A1

公开(公告)日：2009-07-30

申请号：US12022860

申请日：2008-01-30

申请人： Darin A. Chan ,  Yi Zou ,  Yuansheng Ma ,  Marilyn Wright ,  Mark Michael ,  Donna Michael

发明人： Darin A. Chan ,  Yi Zou ,  Yuansheng Ma ,  Marilyn Wright ,  Mark Michael ,  Donna Michael

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/10

摘要： The present invention generates model scenarios of semiconductor chip design and uses interpolation and Monte Carlo, with random number generation inputs, techniques to iteratively assess the models for a more comprehensive and accurate assessment of design space, and evaluation under projected manufacturing conditions. This evaluation information is then incorporated into design rules in order to improve yield.

摘要翻译： 本发明生成半导体芯片设计的模型场景，并使用插值和蒙特卡罗随机数生成输入，迭代评估模型，以更全面，准确地评估设计空间，并在预计制造条件下进行评估。 然后将该评估信息并入设计规则以提高产量。

公开(公告)号：US07023059B1

公开(公告)日：2006-04-04

申请号：US10791094

申请日：2004-03-01

申请人： Darin A. Chan ,  Simon Siu-Sing Chan ,  Jeffrey P. Patton ,  Jacques J. Bertrand

发明人： Darin A. Chan ,  Simon Siu-Sing Chan ,  Jeffrey P. Patton ,  Jacques J. Bertrand

IPC分类号： H01L29/94

CPC分类号： H01L29/66636 ,  H01L21/76897 ,  H01L29/665 ,  H01L29/6653

摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain regions and on the gate. Trenches are formed in the semiconductor substrate around the gate. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed to the silicide.

摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 在源极/漏极区域和栅极上形成硅化物。 在栅极周围的半导体衬底中形成沟槽。 在半导体衬底上沉积层间电介质，然后与硅化物形成接触。

公开(公告)号：US06566176B1

公开(公告)日：2003-05-20

申请号：US10196644

申请日：2002-07-16

申请人： Darin A. Chan

发明人： Darin A. Chan

IPC分类号： H01L2184

CPC分类号： H01L29/66772 ,  H01L21/743 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78621

摘要： A transistor device on an SOI wafer includes a metal connect that is in contact with an underside (a bottom surface) of a body of the device. A part of the metal connect is between an active semiconductor region of the device and an underlying buried insulator layer. The metal connect is also in contact with a source of the device, thereby providing some electrical coupling between the source and the body, and as a result reducing or eliminating floating body effects in the device. A method of forming the metal interconnect includes etching away part of the buried insulator layer, for example by lateral etching or isotropic etching, and filling with metal, for example by chemical vapor deposition.

公开(公告)号：US6127261A

公开(公告)日：2000-10-03

申请号：US559054

申请日：1995-11-16

申请人： Minh Van Ngo ,  Darin A. Chan

发明人： Minh Van Ngo ,  Darin A. Chan

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/316

CPC分类号： H01L21/76801 ,  H01L21/76829 ,  H01L23/5329 ,  H01L2924/0002

摘要： A method of depositing a premetal dielectric layer involves deposition of a triple premetal dielectric layer in in-situ deposition in a single fabrication tool with each subsequent layer being deposited after a previous layer with no intervening handling step. Thus, no intervening cleaning steps or other intermediate steps are performed.

摘要翻译： 沉积预金属介电层的方法包括在单一制造工具中原位沉积中沉积三重预金属介电层，其中每个后续层在先前层之后沉积，而不需要中间处理步骤。 因此，不执行介入的清洁步骤或其他中间步骤。

公开(公告)号：US6060404A

公开(公告)日：2000-05-09

申请号：US924130

申请日：1997-09-05

申请人： Minh Van Ngo ,  Darin A. Chan ,  Sey-Ping Sun ,  Terri Kitson ,  John Caffall

发明人： Minh Van Ngo ,  Darin A. Chan ,  Sey-Ping Sun ,  Terri Kitson ,  John Caffall

IPC分类号： H01L21/314 ,  H01L21/768 ,  H01L21/72

CPC分类号： H01L21/76801 ,  H01L21/3144 ,  H01L21/76834 ,  H01L21/76895

摘要： An in-situ deposition method allows for the forming of a dielectric layer suitable for use in forming a conductive path in a semiconductor wafer. The method includes depositing a thin SiO.sub.x N.sub.y stop layer on top of a semiconductor wafer within a chemical vapor deposition (CVD) reactor chamber having a low pressure, maintaining the low pressure following the deposition of the SiO.sub.x N.sub.y stop layer, and then depositing a thick TEOS oxide dielectric layer on the SiO.sub.x N.sub.y stop layer within the CVD reactor chamber. The in-situ deposition process reduces outgassing defects that would normally form at the interface between the SiON stop layer and the TEOS oxide dielectric layer.

摘要翻译： 原位沉积方法允许形成适合用于在半导体晶片中形成导电路径的电介质层。 该方法包括在具有低压的化学气相沉积（CVD）反应器室内的半导体晶片的顶部上沉积薄的SiOxNy阻挡层，保持在沉积SiO x N y终止层之后的低压，然后沉积厚的TEOS氧化物 在CVD反应器室内的SiOxNy停止层上的介电层。 原位沉积过程减少了通常在SiON阻挡层和TEOS氧化物介电层之间的界面处形成的除气缺陷。