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公开(公告)号：US20080310495A1
公开(公告)日：2008-12-18
申请号：US11761586
申请日：2007-06-12
IPC分类号： H04L27/01
CPC分类号： H04L25/03057 , H04L25/067 , H04L2025/0349
摘要： A decision feedback equalizer (DFE) and method include at least two paths. Each path includes the following. An adder is configured to sum an input with a first feedback tap fed back from a different path. A latch is coupled to the adder to receive a summation signal as input. The latch includes a transparent state, and an output of the latch is employed as the first tap in a feedback path to an adder of a different path, wherein a partially resolved first tap in the feedback path is employed during the transparent state to provide a soft decision to supply correction information in advance of a hard decision of the latch.
摘要翻译： 决策反馈均衡器（DFE）和方法包括至少两个路径。 每个路径包括以下内容。 加法器被配置为将输入与从不同路径反馈的第一反馈分接相加。 锁存器耦合到加法器以接收加法信号作为输入。 锁存器包括透明状态，并且锁存器的输出被用作到到不同路径的加法器的反馈路径中的第一抽头，其中在透明状态期间采用反馈路径中的部分分辨的第一抽头以提供一个 软判决在锁存器的硬判决之前提供校正信息。
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公开(公告)号：US07822114B2
公开(公告)日：2010-10-26
申请号：US11761586
申请日：2007-06-12
IPC分类号： H03H7/30
CPC分类号： H04L25/03057 , H04L25/067 , H04L2025/0349
摘要： A decision feedback equalizer (DFE) and method include at least two paths. Each path includes the following. An adder is configured to sum an input with a first feedback tap fed back from a different path. A latch is coupled to the adder to receive a summation signal as input. The latch includes a transparent state, and an output of the latch is employed as the first tap in a feedback path to an adder of a different path, wherein a partially resolved first tap in the feedback path is employed during the transparent state to provide a soft decision to supply correction information in advance of a hard decision of the latch.
摘要翻译： 决策反馈均衡器（DFE）和方法包括至少两个路径。 每个路径包括以下内容。 加法器被配置为将输入与从不同路径反馈的第一反馈分接相加。 锁存器耦合到加法器以接收加法信号作为输入。 锁存器包括透明状态，并且锁存器的输出被用作到到不同路径的加法器的反馈路径中的第一抽头，其中在透明状态期间采用反馈路径中的部分分辨的第一抽头以提供一个 软判决在锁存器的硬判决之前提供校正信息。
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公开(公告)号：US08183948B2
公开(公告)日：2012-05-22
申请号：US12702798
申请日：2010-02-09
申请人： Herschel A. Ainspan , John F. Bulzacchelli , Daniel J. Friedman , Ankush Goel , Alexander V. Rylyakov
发明人： Herschel A. Ainspan , John F. Bulzacchelli , Daniel J. Friedman , Ankush Goel , Alexander V. Rylyakov
CPC分类号： H03B5/1212 , H03B5/1215 , H03B5/1228 , H03B5/1253 , H03B5/1256 , H03B5/1265 , H03B2200/0088 , H03L7/099 , H03L7/10 , H03L7/18 , H03L2207/06 , H03L2207/50
摘要： A design for an oscillator, and a PLL incorporating such an oscillator, which takes up little physical area but maintains a large tuning range and low phase noise. Two LC-tanks are nested and switched. Through tuning the inactive tank, the range of the active tank may be increased and finer tuning becomes possible.
摘要翻译： 振荡器的设计，以及包含这种振荡器的PLL，其占用很小的物理面积，但保持较大的调谐范围和低的相位噪声。 两个LC坦克被嵌套和切换。 通过调节不活动的水箱，可以增加活动水箱的范围，并可以进行更精细的调节。
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公开(公告)号：US20110063038A1
公开(公告)日：2011-03-17
申请号：US12702798
申请日：2010-02-09
申请人： Herschel A. Ainspan , John F. Bulzacchelli , Daniel J. Friedman , Ankush Goel , Alexander V. Rylyakov
发明人： Herschel A. Ainspan , John F. Bulzacchelli , Daniel J. Friedman , Ankush Goel , Alexander V. Rylyakov
CPC分类号： H03B5/1212 , H03B5/1215 , H03B5/1228 , H03B5/1253 , H03B5/1256 , H03B5/1265 , H03B2200/0088 , H03L7/099 , H03L7/10 , H03L7/18 , H03L2207/06 , H03L2207/50
摘要： A design for an oscillator, and a PLL incorporating such an oscillator, which takes up little physical area but maintains a large tuning range and low phase noise. Two LC-tanks are nested and switched. Through tuning the inactive tank, the range of the active tank may be increased and finer tuning becomes possible.
摘要翻译： 振荡器的设计，以及包含这种振荡器的PLL，其占用很小的物理面积，但保持较大的调谐范围和低的相位噪声。 两个LC坦克被嵌套和切换。 通过调节不活动的水箱，可以增加活动水箱的范围，并可以进行更精细的调节。
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5.发明申请DUAL-LOOP VOLTAGE REGULATOR ARCHITECTURE WITH HIGH DC ACCURACY AND FAST RESPONSE TIME 有权具有高直流精度和快速响应时间的双环电压调节器架构公开(公告)号：US20120153910A1
公开(公告)日：2012-06-21
申请号：US13213578
申请日：2011-08-19
申请人： John F. Bulzacchelli , Carrie E. Cox , Zeynep Toprak-Deniz , Daniel J. Friedman , Joseph A. Iadanza , Todd M. Rasmus
发明人： John F. Bulzacchelli , Carrie E. Cox , Zeynep Toprak-Deniz , Daniel J. Friedman , Joseph A. Iadanza , Todd M. Rasmus
IPC分类号： G05F1/10
CPC分类号： G05F1/575
摘要： Dual-loop voltage regulator circuits and methods in which a dual-loop voltage regulation framework is implemented with a first inner loop having a bang-bang voltage regulator to achieve nearly instantaneous response time, and a second outer loop, which is slower in operating speed than the first inner loop, to controllably adjust a trip point of the bang-bang voltage regulator to achieve high DC accuracy.
摘要翻译： 双环路电压调节器电路和方法，其中使用具有爆轰电压调节器的第一内环实现双回路电压调节框架以实现几乎瞬时的响应时间，以及第二外环，其操作速度较慢 比第一个内环，可控地调节砰砰电压调节器的跳闸点，以实现高直流精度。
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6.发明授权Optimal dithering of a digitally controlled oscillator with clock dithering for gain and bandwidth control 有权具有时钟抖动的数字控制振荡器的最佳抖动，用于增益和带宽控制公开(公告)号：US08138840B2
公开(公告)日：2012-03-20
申请号：US12358736
申请日：2009-01-23
申请人： Herschel A. Ainspan , John F. Bulzacchelli , Zeynep Toprak Deniz , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Herschel A. Ainspan , John F. Bulzacchelli , Zeynep Toprak Deniz , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
摘要： A digital phase locked loop (DPLL) and method include an adjustable delay line configured to receive a reference clock as an input and to output a dithered reference clock signal. A phase and frequency detector (PFD) is configured to compare the dithered reference clock signal with a feedback clock signal to determine phase and frequency differences between the dithered reference clock signal and the feedback clock signal. A digitally controlled oscillator (DCO) is configured to receive early or late determinations from the PFD to adjust an output in accordance therewith, wherein the dithered reference clock signal distributes jitter response to enhance overall operation of the DPLL.
摘要翻译： 数字锁相环（DPLL）和方法包括可调延迟线，其配置为接收参考时钟作为输入并输出抖动参考时钟信号。 相位和频率检测器（PFD）被配置为将抖动参考时钟信号与反馈时钟信号进行比较，以确定抖动参考时钟信号和反馈时钟信号之间的相位和频率差。 数字控制振荡器（DCO）被配置为接收来自PFD的早期或晚期确定以根据其调整输出，其中抖动参考时钟信号分配抖动响应以增强DPLL的整体操作。
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公开(公告)号：US20090252215A1
公开(公告)日：2009-10-08
申请号：US12061268
申请日：2008-04-02
IPC分类号： H04L27/01
CPC分类号： H04L25/03019 , H04L25/03031
摘要： A decision feedback equalizer (DFE) and method including a branch coupled to an input and including a sample-and-hold element configured to receive and sample a received input signal from the input and a current-integrating summer. The current-integrating summer is coupled to an output of the sample-and-hold element. The summer is configured to receive and sum currents representing at least one previous decision and an input sample. The at least one previous decision and the input sample are integrated onto a node, wherein the input sample is held constant during an integration period, thereby mitigating the effects of input transitions on an output of the summer.
摘要翻译： 一种判决反馈均衡器（DFE）和方法，包括耦合到输入端并包括采样保持元件的分支，所述采样保持元件被配置为从所述输入端接收和采样所接收的输入信号以及电流积分夏令。 电流积分加法器与采样保持元件的输出耦合。 夏天被配置为接收并且表示至少一个先前决定和输入样本的和电流。 至少一个先前的决定和输入样本被集成到节点上，其中输入样本在积分期间保持不变，从而减轻输入转换对夏季输出的影响。
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公开(公告)号：US08779865B2
公开(公告)日：2014-07-15
申请号：US13350981
申请日：2012-01-16
申请人： Herschel A. Ainspan , John F. Bulzacchelli , Daniel J. Friedman , Ankush Goel , Alexander V. Rylyakov
发明人： Herschel A. Ainspan , John F. Bulzacchelli , Daniel J. Friedman , Ankush Goel , Alexander V. Rylyakov
CPC分类号： H03B5/1212 , H03B5/1215 , H03B5/1228 , H03B5/1253 , H03B5/1256 , H03B5/1265 , H03B2200/0088 , H03L7/099 , H03L7/10 , H03L7/18 , H03L2207/06 , H03L2207/50
摘要： A design for an oscillator, and a PLL incorporating such an oscillator, which takes up little physical area but maintains a large tuning range and low phase noise. Two LC-tanks are nested and switched. Through tuning the inactive tank, the range of the active tank may be increased and finer tuning becomes possible.
摘要翻译： 振荡器的设计，以及包含这种振荡器的PLL，其占用很小的物理面积，但保持较大的调谐范围和低的相位噪声。 两个LC坦克被嵌套和切换。 通过调节不活动的水箱，可以增加活动水箱的范围，并可以进行更精细的调节。
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公开(公告)号：US08085841B2
公开(公告)日：2011-12-27
申请号：US12061268
申请日：2008-04-02
IPC分类号： H04L27/01
CPC分类号： H04L25/03019 , H04L25/03031
摘要： A decision feedback equalizer (DFE) and method including a branch coupled to an input and including a sample-and-hold element configured to receive and sample a received input signal from the input and a current-integrating summer. The current-integrating summer is coupled to an output of the sample-and-hold element. The summer is configured to receive and sum currents representing at least one previous decision and an input sample. The at least one previous decision and the input sample are integrated onto a node, wherein the input sample is held constant during an integration period, thereby mitigating the effects of input transitions on an output of the summer.
摘要翻译： 一种判决反馈均衡器（DFE）和方法，包括耦合到输入端并包括采样保持元件的分支，所述采样保持元件被配置为从所述输入端接收和采样所接收的输入信号以及电流积分夏令。 电流积分加法器与采样保持元件的输出耦合。 夏天被配置为接收并且表示至少一个先前决定和输入样本的和电流。 至少一个先前的决定和输入样本被集成到节点上，其中输入样本在积分期间保持不变，从而减轻输入转换对夏季输出的影响。
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10.发明申请OPTIMAL DITHERING OF A DIGITALLY CONTROLLED OSCILLATOR WITH CLOCK DITHERING FOR GAIN AND BANDWIDTH CONTROL 有权数字控制振荡器的最佳抖动，具有时钟抖动，用于增益和带宽控制公开(公告)号：US20100188158A1
公开(公告)日：2010-07-29
申请号：US12358736
申请日：2009-01-23
申请人： Herschel A. Ainspan , John F. Bulzacchelli , Zeynep Toprak Deniz , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Herschel A. Ainspan , John F. Bulzacchelli , Zeynep Toprak Deniz , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03L7/099
摘要： A digital phase locked loop (DPLL) and method include an adjustable delay line configured to receive a reference clock as an input and to output a dithered reference clock signal. A phase and frequency detector (PFD) is configured to compare the dithered reference clock signal with a feedback clock signal to determine phase and frequency differences between the dithered reference clock signal and the feedback clock signal. A digitally controlled oscillator (DCO) is configured to receive early or late determinations from the PFD to adjust an output in accordance therewith, wherein the dithered reference clock signal distributes jitter response to enhance overall operation of the DPLL.
摘要翻译： 数字锁相环（DPLL）和方法包括可调延迟线，其配置为接收参考时钟作为输入并输出抖动参考时钟信号。 相位和频率检测器（PFD）被配置为将抖动参考时钟信号与反馈时钟信号进行比较，以确定抖动参考时钟信号和反馈时钟信号之间的相位和频率差。 数字控制振荡器（DCO）被配置为接收来自PFD的早期或晚期确定以根据其调整输出，其中抖动参考时钟信号分配抖动响应以增强DPLL的整体操作。
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