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1.发明授权Timing recovery method and apparatus for an input/output bus with link redundancy 有权具有链路冗余的输入/输出总线的定时恢复方法和装置公开(公告)号：US08774228B2
公开(公告)日：2014-07-08
申请号：US13157968
申请日：2011-06-10
IPC分类号： H04J3/06
CPC分类号： H04L7/10 , H04L7/0337
摘要： Methods and apparatus are provided for timing recovery for an input/output bus with link redundancy. A parallel input/output interface receiver includes a plurality of data receivers, each configured to respectively receive input data from a respective one of n+m channels, where n is an integer greater than one and m is an integer greater than or equal to one. The input data is non-calibration data for the n channels and is calibration data for the m channels. The interface receiver further includes a first phase adjustor configured to provide a first clock signal to the plurality of data receivers for sampling of only the non-calibration data at any given time, and a second phase adjustor configured to provide a second clock signal to the plurality of data receivers for sampling of only the calibration data at any given time.
摘要翻译： 提供了用于具有链路冗余的输入/输出总线的定时恢复的方法和装置。 并行输入/输出接口接收器包括多个数据接收器，每个数据接收器被配置为分别从n + m个通道中的相应一个通道接收输入数据，其中n是大于1的整数，并且m是大于或等于1的整数 。 输入数据是n个通道的非校准数据，是m个通道的校准数据。 接口接收器还包括第一相位调节器，其被配置为向多个数据接收器提供第一时钟信号，用于在任何给定时间仅对非校准数据进行采样，以及第二相位调整器，被配置为向第 多个数据接收器，用于在任何给定时间仅对校准数据进行采样。
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2.发明申请TIMING RECOVERY METHOD AND APPARATUS FOR AN INPUT/OUTPUT BUS WITH LINK REDUNDANCY 有权具有链路冗余的输入/输出总线的时序恢复方法和装置公开(公告)号：US20120314721A1
公开(公告)日：2012-12-13
申请号：US13157968
申请日：2011-06-10
CPC分类号： H04L7/10 , H04L7/0337
摘要： Methods and apparatus are provided for timing recovery for an input/output bus with link redundancy. A parallel input/output interface receiver includes a plurality of data receivers, each configured to respectively receive input data from a respective one of n+m channels, where n is an integer greater than one and m is an integer greater than or equal to one. The input data is non-calibration data for the n channels and is calibration data for the m channels. The interface receiver further includes a first phase adjustor configured to provide a first clock signal to the plurality of data receivers for sampling of only the non-calibration data at any given time, and a second phase adjustor configured to provide a second clock signal to the plurality of data receivers for sampling of only the calibration data at any given time.
摘要翻译： 提供了用于具有链路冗余的输入/输出总线的定时恢复的方法和装置。 并行输入/输出接口接收器包括多个数据接收器，每个数据接收器被配置为分别从n + m个通道中的相应一个通道接收输入数据，其中n是大于1的整数，并且m是大于或等于1的整数 。 输入数据是n个通道的非校准数据，是m个通道的校准数据。 接口接收器还包括第一相位调节器，其被配置为向多个数据接收器提供第一时钟信号，用于在任何给定时间仅对非校准数据进行采样，以及第二相位调整器，被配置为向第 多个数据接收器，用于在任何给定时间仅对校准数据进行采样。
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公开(公告)号：US08085841B2
公开(公告)日：2011-12-27
申请号：US12061268
申请日：2008-04-02
IPC分类号： H04L27/01
CPC分类号： H04L25/03019 , H04L25/03031
摘要： A decision feedback equalizer (DFE) and method including a branch coupled to an input and including a sample-and-hold element configured to receive and sample a received input signal from the input and a current-integrating summer. The current-integrating summer is coupled to an output of the sample-and-hold element. The summer is configured to receive and sum currents representing at least one previous decision and an input sample. The at least one previous decision and the input sample are integrated onto a node, wherein the input sample is held constant during an integration period, thereby mitigating the effects of input transitions on an output of the summer.
摘要翻译： 一种判决反馈均衡器（DFE）和方法，包括耦合到输入端并包括采样保持元件的分支，所述采样保持元件被配置为从所述输入端接收和采样所接收的输入信号以及电流积分夏令。 电流积分加法器与采样保持元件的输出耦合。 夏天被配置为接收并且表示至少一个先前决定和输入样本的和电流。 至少一个先前的决定和输入样本被集成到节点上，其中输入样本在积分期间保持不变，从而减轻输入转换对夏季输出的影响。
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公开(公告)号：US20090252215A1
公开(公告)日：2009-10-08
申请号：US12061268
申请日：2008-04-02
IPC分类号： H04L27/01
CPC分类号： H04L25/03019 , H04L25/03031
摘要： A decision feedback equalizer (DFE) and method including a branch coupled to an input and including a sample-and-hold element configured to receive and sample a received input signal from the input and a current-integrating summer. The current-integrating summer is coupled to an output of the sample-and-hold element. The summer is configured to receive and sum currents representing at least one previous decision and an input sample. The at least one previous decision and the input sample are integrated onto a node, wherein the input sample is held constant during an integration period, thereby mitigating the effects of input transitions on an output of the summer.
摘要翻译： 一种判决反馈均衡器（DFE）和方法，包括耦合到输入端并包括采样保持元件的分支，所述采样保持元件被配置为从所述输入端接收和采样所接收的输入信号以及电流积分夏令。 电流积分加法器与采样保持元件的输出耦合。 夏天被配置为接收并且表示至少一个先前决定和输入样本的和电流。 至少一个先前的决定和输入样本被集成到节点上，其中输入样本在积分期间保持不变，从而减轻输入转换对夏季输出的影响。
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5.发明授权Calibration of multiple parallel data communications lines for high skew conditions 失效多个并行数据通信线路的校准用于高偏斜条件公开(公告)号：US08681839B2
公开(公告)日：2014-03-25
申请号：US12912883
申请日：2010-10-27
申请人： John F. Bulzacchelli , Timothy O. Dickson , Frank D. Ferraiolo , Robert J. Reese , Michael B. Spear
发明人： John F. Bulzacchelli , Timothy O. Dickson , Frank D. Ferraiolo , Robert J. Reese , Michael B. Spear
CPC分类号： H04L25/14 , G06F2213/0038 , H04L7/0025 , H04L7/0337
摘要： A parallel data link includes a redundant line. A bank of switches permits any arbitrary line of the link to be enabled or disabled for carrying functional data, each line being dynamically calibrated in turn by disabling the line and allowing other lines to carry the functional data. The switches are located downstream of alignment mechanisms so that data input to the switches is compensated for data skew. Preferably, receiver synchronization circuitry in each line operates in a respective independent clock domain, while the switches and calibration mechanism operate in a common clock domain. Preferably, the receiver synchronization circuits provide an adjustable delay corresponding to a variable number of clock cycles to align the outputs of the receiver synchronization circuits with respect to one another, which can accommodate high data skew.
摘要翻译： 并行数据链路包括冗余线路。 一组交换机允许链路的任意任意行被启用或禁用以承载功能数据，每行通过禁用线路并允许其他线路携带功能数据依次被动态地校准。 开关位于对准机构的下游，以便数据输入到开关的数据偏移。 优选地，每行中的接收器同步电路在相应的独立时钟域中操作，而开关和校准机构在公共时钟域中操作。 优选地，接收机同步电路提供对应于可变数量的时钟周期的可调节延迟，以使接收机同步电路的输出相对于彼此对准，这可以适应高数据偏移。
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6.发明申请Calibration of Multiple Parallel Data Communications Lines for High Skew Conditions 失效多个并行数据通信线路的校准用于高歪斜条件公开(公告)号：US20120106687A1
公开(公告)日：2012-05-03
申请号：US12912883
申请日：2010-10-27
申请人： John F. Bulzacchelli , Timothy O. Dickson , Frank D. Ferraiolo , Robert J. Reese , Michael B. Spear
发明人： John F. Bulzacchelli , Timothy O. Dickson , Frank D. Ferraiolo , Robert J. Reese , Michael B. Spear
IPC分类号： H04L7/00
CPC分类号： H04L25/14 , G06F2213/0038 , H04L7/0025 , H04L7/0337
摘要： A parallel data link includes a redundant line. A bank of switches permits any arbitrary line of the link to be enabled or disabled for carrying functional data, each line being dynamically calibrated in turn by disabling the line and allowing other lines to carry the functional data. The switches are located downstream of alignment mechanisms so that data input to the switches is compensated for data skew. Preferably, receiver synchronization circuitry in each line operates in a respective independent clock domain, while the switches and calibration mechanism operate in a common clock domain. Preferably, the receiver synchronization circuits provide an adjustable delay corresponding to a variable number of clock cycles to align the outputs of the receiver synchronization circuits with respect to one another, which can accommodate high data skew.
摘要翻译： 并行数据链路包括冗余线路。 一组交换机允许链路的任意任意行被启用或禁用以承载功能数据，每行通过禁用线路并允许其他线路携带功能数据依次被动态地校准。 开关位于对准机构的下游，以便数据输入到开关的数据偏移。 优选地，每行中的接收器同步电路在相应的独立时钟域中操作，而开关和校准机构在公共时钟域中操作。 优选地，接收机同步电路提供对应于可变数量的时钟周期的可调节延迟，以使接收机同步电路的输出相对于彼此对准，这可以适应高数据偏移。
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公开(公告)号：US20140056345A1
公开(公告)日：2014-02-27
申请号：US13591666
申请日：2012-08-22
CPC分类号： H04L25/03057
摘要： Equalization techniques are provided for high-speed data communications and, more specifically, DFE (decision feedback equalizer) circuits and methods are provided which implement a high-order continuous time filter in a DFE feedback path to emulate structured elements of a channel response.
摘要翻译： 提供了用于高速数据通信的均衡技术，更具体地，提供了DFE（判决反馈均衡器）电路和方法，其在DFE反馈路径中实现高阶连续时间滤波器以模拟信道响应的结构化元素。
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8.发明授权公开(公告)号：US09411750B2
公开(公告)日：2016-08-09
申请号：US13561446
申请日：2012-07-30
CPC分类号： G06F15/17318 , G06F9/00 , G06F11/3058 , G06F13/00 , G06F13/1673 , G06F13/24 , G06F13/4217 , G06F13/4282 , G06F15/803 , G06F19/00 , H04B1/38 , H04L12/56 , Y02D10/14 , Y02D10/151
摘要： A calibratable communications link includes multiple parallel lines. Calibration is performed at dynamically variable and/or interruptible intervals determined by an automated mechanism. Calibration is preferably initiated responsive to a command generated by an executable software process, which initiates calibration responsive to detection of a probable impending need as indicated by, e.g., temperature change, calibrated parameter drift, error rate, etc. Calibration is also preferably initiated according to probable minimal disruption of device function, as indicated by low activity level. Furthermore, in one aspect calibration may be temporarily suspended to transmit data and then resumed.
摘要翻译： 可校准通信链路包括多条平行线。 由自动机制确定的动态变量和/或可中断间隔进行校准。 校准优选地响应于由可执行软件过程产生的命令来启动，该指令响应于可能的即将发生的需求的检测而启动校准，如由温度变化，校准参数漂移，错误率等指示的。也优选地根据 可能的最小的设备功能中断，如低活动水平所示。 此外，在一个方面，可以临时暂停校准以发送数据，然后恢复。
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公开(公告)号：US08842722B2
公开(公告)日：2014-09-23
申请号：US13591403
申请日：2012-08-22
IPC分类号： H03H7/30
CPC分类号： H04L25/03057
摘要： Equalization techniques are provided for high-speed data communications and, more specifically, DFE (decision feedback equalizer) circuits and methods are provided which implement a high-order continuous time filter in a DFE feedback path to emulate structured elements of a channel response.
摘要翻译： 提供了用于高速数据通信的均衡技术，更具体地，提供了DFE（判决反馈均衡器）电路和方法，其在DFE反馈路径中实现高阶连续时间滤波器以模拟信道响应的结构化元素。
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公开(公告)号：US20140056344A1
公开(公告)日：2014-02-27
申请号：US13591403
申请日：2012-08-22
CPC分类号： H04L25/03057
摘要： Equalization techniques are provided for high-speed data communications and, more specifically, DFE (decision feedback equalizer) circuits and methods are provided which implement a high-order continuous time filter in a DFE feedback path to emulate structured elements of a channel response.
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