公开(公告)号：US08774228B2

公开(公告)日：2014-07-08

申请号：US13157968

申请日：2011-06-10

申请人： John F. Bulzacchelli ,  Timothy O. Dickson ,  Daniel J. Friedman ,  Yong Liu ,  Sergey V. Rylov

发明人： John F. Bulzacchelli ,  Timothy O. Dickson ,  Daniel J. Friedman ,  Yong Liu ,  Sergey V. Rylov

IPC分类号： H04J3/06

CPC分类号： H04L7/10 ,  H04L7/0337

摘要： Methods and apparatus are provided for timing recovery for an input/output bus with link redundancy. A parallel input/output interface receiver includes a plurality of data receivers, each configured to respectively receive input data from a respective one of n+m channels, where n is an integer greater than one and m is an integer greater than or equal to one. The input data is non-calibration data for the n channels and is calibration data for the m channels. The interface receiver further includes a first phase adjustor configured to provide a first clock signal to the plurality of data receivers for sampling of only the non-calibration data at any given time, and a second phase adjustor configured to provide a second clock signal to the plurality of data receivers for sampling of only the calibration data at any given time.

摘要翻译： 提供了用于具有链路冗余的输入/输出总线的定时恢复的方法和装置。 并行输入/输出接口接收器包括多个数据接收器，每个数据接收器被配置为分别从n + m个通道中的相应一个通道接收输入数据，其中n是大于1的整数，并且m是大于或等于1的整数 。 输入数据是n个通道的非校准数据，是m个通道的校准数据。 接口接收器还包括第一相位调节器，其被配置为向多个数据接收器提供第一时钟信号，用于在任何给定时间仅对非校准数据进行采样，以及第二相位调整器，被配置为向第 多个数据接收器，用于在任何给定时间仅对校准数据进行采样。

公开(公告)号：US20120314721A1

公开(公告)日：2012-12-13

申请号：US13157968

申请日：2011-06-10

申请人： JOHN F. BULZACCHELLI ,  Timothy O. Dickson ,  Daniel J. Friedman ,  Yong Liu ,  Sergey V. Rylov

发明人： JOHN F. BULZACCHELLI ,  Timothy O. Dickson ,  Daniel J. Friedman ,  Yong Liu ,  Sergey V. Rylov

IPC分类号： H04L7/00 ,  H04J3/06

CPC分类号： H04L7/10 ,  H04L7/0337

摘要： Methods and apparatus are provided for timing recovery for an input/output bus with link redundancy. A parallel input/output interface receiver includes a plurality of data receivers, each configured to respectively receive input data from a respective one of n+m channels, where n is an integer greater than one and m is an integer greater than or equal to one. The input data is non-calibration data for the n channels and is calibration data for the m channels. The interface receiver further includes a first phase adjustor configured to provide a first clock signal to the plurality of data receivers for sampling of only the non-calibration data at any given time, and a second phase adjustor configured to provide a second clock signal to the plurality of data receivers for sampling of only the calibration data at any given time.

摘要翻译： 提供了用于具有链路冗余的输入/输出总线的定时恢复的方法和装置。 并行输入/输出接口接收器包括多个数据接收器，每个数据接收器被配置为分别从n + m个通道中的相应一个通道接收输入数据，其中n是大于1的整数，并且m是大于或等于1的整数 。 输入数据是n个通道的非校准数据，是m个通道的校准数据。 接口接收器还包括第一相位调节器，其被配置为向多个数据接收器提供第一时钟信号，用于在任何给定时间仅对非校准数据进行采样，以及第二相位调整器，被配置为向第 多个数据接收器，用于在任何给定时间仅对校准数据进行采样。

公开(公告)号：US20140063925A1

公开(公告)日：2014-03-06

申请号：US13434739

申请日：2012-03-29

申请人： Daniel J. Friedman ,  Seongwon Kim ,  Yong Liu ,  Bipin Rajendran

发明人： Daniel J. Friedman ,  Seongwon Kim ,  Yong Liu ,  Bipin Rajendran

IPC分类号： G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0085 ,  G11C2013/0088 ,  G11C2013/0092 ,  G11C2213/79

摘要： Embodiments of the present invention provide a device comprising a plurality of phase change memory cells, a word line, and a plurality of bit lines. Each phase change memory cell is coupled to a corresponding transistor. Each transistor is coupled to the word line. Each bit line is coupled to a phase change memory cell of the device. The device further comprises a programming circuit configured to program at least one phase change memory cell to the SET state by selectively applying a two-stage waveform to the word line and the bit lines of the device. In a first stage, a first predetermined low voltage and a first predetermined high voltage are applied at the word line and the bit lines, respectively. In a second stage, a second predetermined high voltage and a predetermined voltage with decreasing amplitude are applied at the word line and the bit lines, respectively.

摘要翻译： 本发明的实施例提供一种包括多个相变存储单元，字线和多个位线的装置。 每个相变存储单元耦合到相应的晶体管。 每个晶体管耦合到字线。 每个位线耦合到器件的相变存储器单元。 该装置还包括编程电路，其被配置为通过选择性地将两级波形应用于该装置的字线和位线来将至少一个相变存储器单元编程到SET状态。 在第一阶段中，分别在字线和位线处施加第一预定低电压和第一预定高电压。 在第二级中，分别在字线和位线处施加具有降低幅度的第二预定高电压和预定电压。

公开(公告)号：US08898097B2

公开(公告)日：2014-11-25

申请号：US13587594

申请日：2012-08-16

申请人： Bernard V. Brezzo ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

发明人： Bernard V. Brezzo ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

IPC分类号： G06N3/063 ,  G06N3/04

CPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/049 ,  G06N3/082

摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

摘要翻译： 提供可重构神经网络电路。 可重构神经网络电路包括电子突触阵列，其包括互连多个数字电子神经元的多个突触。 每个神经元包括积分器，其对输入尖峰进行积分，并且当集成输入超过阈值时产生信号。 电路还包括用于重新配置突触阵列的控制模块。 控制模块包括控制电路操作的定时的全局最终状态机，以及允许加标神经元依次访问突触阵列的优先编码器。

公开(公告)号：US08856055B2

公开(公告)日：2014-10-07

申请号：US13083414

申请日：2011-04-08

申请人： Bernard V. Brezzo ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

发明人： Bernard V. Brezzo ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

IPC分类号： G06N3/063 ,  G06N3/04

CPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/049 ,  G06N3/082

摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

公开(公告)号：US20120317062A1

公开(公告)日：2012-12-13

申请号：US13587594

申请日：2012-08-16

申请人： Bernard V. BREZZO ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

发明人： Bernard V. BREZZO ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

IPC分类号： G06N3/08

CPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/049 ,  G06N3/082

摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

摘要翻译： 提供可重构神经网络电路。 可重构神经网络电路包括电子突触阵列，其包括互连多个数字电子神经元的多个突触。 每个神经元包括积分器，其对输入尖峰进行积分，并且当集成输入超过阈值时产生信号。 电路还包括用于重新配置突触阵列的控制模块。 控制模块包括控制电路操作的定时的全局最终状态机，以及允许加标神经元依次访问突触阵列的优先编码器。

公开(公告)号：US20080191746A1

公开(公告)日：2008-08-14

申请号：US11672737

申请日：2007-02-08

申请人： DANIEL J. FRIEDMAN ,  Yong Liu ,  Woogeun Rhee

发明人： DANIEL J. FRIEDMAN ,  Yong Liu ,  Woogeun Rhee

IPC分类号： H03L7/087 ,  H03L7/085 ,  H03D13/00

CPC分类号： H03D13/004 ,  H03L7/087 ,  H03L7/0896 ,  H03L7/0898 ,  H03L7/095

摘要： An instantaneous phase error detector (IPED) and method includes a first gate configured to logically OR output phase error signals as data to a first latch, and a second gate configured to logically combine the output phase error signals to clock the first latch. A delay element delays to the data to the first latch where the output of the first latch provides instantaneous phase error change information. A second latch is coupled to the output phase error signals to output a lead/lag signal to indicate which of the output phase error signals is leading. A phase-locked loop employing the output of the IPED is also disclosed along with static phase measurement and jitter optimization features.

摘要翻译： 瞬时相位误差检测器（IPED）和方法包括：第一门，被配置为逻辑或输出相位误差信号作为数据到第一锁存器;以及第二门，被配置为逻辑地组合输出相位误差信号以对第一锁存器进行时钟。 延迟元件延迟到第一锁存器的数据，其中第一锁存器的输出提供瞬时相位误差变化信息。 第二锁存器耦合到输出相位误差信号以输出引导/延迟信号以指示输出相位误差信号中的哪一个正在引导。 采用IPED的输出的锁相环还与静态相位测量和抖动优化特征一起公开。

公开(公告)号：US09240789B2

公开(公告)日：2016-01-19

申请号：US13600534

申请日：2012-08-31

申请人： Daniel J. Friedman ,  Yong Liu ,  Jose A. Tierno

发明人： Daniel J. Friedman ,  Yong Liu ,  Jose A. Tierno

IPC分类号： H03K19/0175 ,  H03K19/0185

CPC分类号： H03K19/018521

摘要： A receiver is adapted to receive an input signal having a first voltage swing and to generate an output signal having a second voltage swing, the output signal being indicative of the input signal, the second voltage swing being greater than the first voltage swing. The receiver includes a first sub-rate receiver block and at least a second sub-rate receiver block. A receiver clock is divided into a first sub-rate clock phase and at least a second sub-rate clock phase, the first sub-rate clock phase being used to drive the first sub-rate receiver block and the second sub-rate clock phase being used to drive the second sub-rate receiver block. Each of the first sub-rate receiver block and the second sub-rate receiver block includes at least one gated-diode sense amplifier.

摘要翻译： 接收器适于接收具有第一电压摆幅的输入信号并产生具有第二电压摆幅的输出信号，该输出信号表示输入信号，第二电压摆幅大于第一电压摆幅。 接收机包括第一子速率接收器块和至少第二子速率接收器块。 接收机时钟被分为第一子速率时钟相位和至少第二子速率时钟相位，第一子速率时钟相位用于驱动第一子速率接收机模块和第二子速率时钟相位 用于驱动第二子速率接收器块。 第一子速率接收器块和第二子速率接收器块中的每一个包括至少一个门控二极管读出放大器。

公开(公告)号：US20150303920A1

公开(公告)日：2015-10-22

申请号：US13600534

申请日：2012-08-31

申请人： Daniel J. Friedman ,  Yong Liu ,  Jose A. Tierno

发明人： Daniel J. Friedman ,  Yong Liu ,  Jose A. Tierno

IPC分类号： H03K19/0185

CPC分类号： H03K19/018521

摘要： A receiver is adapted to receive an input signal having a first voltage swing and to generate an output signal having a second voltage swing, the output signal being indicative of the input signal, the second voltage swing being greater than the first voltage swing. The receiver includes a first sub-rate receiver block and at least a second sub-rate receiver block. A receiver clock is divided into a first sub-rate clock phase and at least a second sub-rate clock phase, the first sub-rate clock phase being used to drive the first sub-rate receiver block and the second sub-rate clock phase being used to drive the second sub-rate receiver block. Each of the first sub-rate receiver block and the second sub-rate receiver block includes at least one gated-diode sense amplifier.

摘要翻译： 接收器适于接收具有第一电压摆幅的输入信号并产生具有第二电压摆幅的输出信号，该输出信号表示输入信号，第二电压摆幅大于第一电压摆幅。 接收机包括第一子速率接收器块和至少第二子速率接收器块。 接收机时钟被分为第一子速率时钟相位和至少第二子速率时钟相位，第一子速率时钟相位用于驱动第一子速率接收机模块和第二子速率时钟相位 用于驱动第二子速率接收器块。 第一子速率接收器块和第二子速率接收器块中的每一个包括至少一个门控二极管读出放大器。

公开(公告)号：US20120259804A1

公开(公告)日：2012-10-11

申请号：US13083414

申请日：2011-04-08

申请人： Bernard V. Brezzo ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

发明人： Bernard V. Brezzo ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

IPC分类号： G06N3/04 ,  G06N3/08

CPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/049 ,  G06N3/082

摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.