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    TIMING RECOVERY METHOD AND APPARATUS FOR AN INPUT/OUTPUT BUS WITH LINK REDUNDANCY
    1.
    发明申请
    TIMING RECOVERY METHOD AND APPARATUS FOR AN INPUT/OUTPUT BUS WITH LINK REDUNDANCY 有权
    具有链路冗余的输入/输出总线的时序恢复方法和装置

    公开(公告)号：US20120314721A1

    公开(公告)日：2012-12-13

    申请号：US13157968

    申请日：2011-06-10

    申请人： JOHN F. BULZACCHELLI ,  Timothy O. Dickson ,  Daniel J. Friedman ,  Yong Liu ,  Sergey V. Rylov

    发明人： JOHN F. BULZACCHELLI ,  Timothy O. Dickson ,  Daniel J. Friedman ,  Yong Liu ,  Sergey V. Rylov

    IPC分类号： H04L7/00 ,  H04J3/06

    CPC分类号： H04L7/10 ,  H04L7/0337

    摘要： Methods and apparatus are provided for timing recovery for an input/output bus with link redundancy. A parallel input/output interface receiver includes a plurality of data receivers, each configured to respectively receive input data from a respective one of n+m channels, where n is an integer greater than one and m is an integer greater than or equal to one. The input data is non-calibration data for the n channels and is calibration data for the m channels. The interface receiver further includes a first phase adjustor configured to provide a first clock signal to the plurality of data receivers for sampling of only the non-calibration data at any given time, and a second phase adjustor configured to provide a second clock signal to the plurality of data receivers for sampling of only the calibration data at any given time.

    摘要翻译： 提供了用于具有链路冗余的输入/输出总线的定时恢复的方法和装置。 并行输入/输出接口接收器包括多个数据接收器，每个数据接收器被配置为分别从n + m个通道中的相应一个通道接收输入数据，其中n是大于1的整数，并且m是大于或等于1的整数 。 输入数据是n个通道的非校准数据，是m个通道的校准数据。 接口接收器还包括第一相位调节器，其被配置为向多个数据接收器提供第一时钟信号，用于在任何给定时间仅对非校准数据进行采样，以及第二相位调整器，被配置为向第 多个数据接收器，用于在任何给定时间仅对校准数据进行采样。

    MULTI-TAP DECISION FEEDBACK EQUALIZER (DFE) ARCHITECTURE ELIMINATING CRITICAL TIMING PATH FOR HIGHER-SPEED OPERATION
    3.
    发明申请
    MULTI-TAP DECISION FEEDBACK EQUALIZER (DFE) ARCHITECTURE ELIMINATING CRITICAL TIMING PATH FOR HIGHER-SPEED OPERATION 有权
    多层次决策反馈均衡器（DFE）架构消除了高速运行的关键时序路径

    公开(公告)号：US20090060021A1

    公开(公告)日：2009-03-05

    申请号：US11848477

    申请日：2007-08-31

    申请人： JOHN F. BULZACCHELLI

    发明人： JOHN F. BULZACCHELLI

    IPC分类号： H04L27/22 ,  H03D3/22

    CPC分类号： H04L25/03057

    摘要： A decision feedback equalizer (DFE) and method include summer circuits to add a dynamic feedback signal representing a dynamic feedback tap to a received input and to speculate on a speculative tap. Data slicers are configured to receive outputs of the summer circuits and sample the outputs of the summer circuits. First multiplexers are included, each of which is configured to receive a first input from a corresponding data slicer. Second multiplexers are included, each of which is configured to receive an output of a plurality of the first multiplexers. The second multiplexers have an output fed back to a second input of the first multiplexers, and the second multiplexer output is employed to provide a select signal for a second multiplexer on a different section of the DFE and to drive the dynamic feedback signal to a summer circuit on a same section of the DFE.

    摘要翻译： 判决反馈均衡器（DFE）和方法包括加法电路，以将表示动态反馈抽头的动态反馈信号添加到接收到的输入并推测投机抽头。 数据限幅器配置为接收夏季电路的输出并对夏季电路的输出进行采样。 包括第一多路复用器，每个复用器被配置为从相应的数据限幅器接收第一输入。 包括第二多路复用器，每个复用器被配置为接收多个第一多路复用器的输出。 第二多路复用器具有反馈到第一多路复用器的第二输入的输出，并且第二多路复用器输出用于在DFE的不同部分上为第二多路复用器提供选择信号，并将动态反馈信号驱动到夏季 电路在DFE的同一部分。

    DECISION FEEDBACK EQUALIZER (DFE) ARCHITECTURE
    5.
    发明申请
    DECISION FEEDBACK EQUALIZER (DFE) ARCHITECTURE 有权
    决策反馈均衡器（DFE）架构

    公开(公告)号：US20080187036A1

    公开(公告)日：2008-08-07

    申请号：US11672270

    申请日：2007-02-07

    申请人： MATTHEW J. PARK ,  JOHN F. BULZACCHELLI

    发明人： MATTHEW J. PARK ,  JOHN F. BULZACCHELLI

    IPC分类号： H04L27/01

    CPC分类号： H04L25/03146 ,  H04L25/03878 ,  H04L2025/03356 ,  H04L2025/03445

    摘要： A decision feedback equalizer (DFE) and method includes summer circuits to add a dynamic feedback signal representing an h2 tap to a received input and to speculate on an h1 tap. Data slicers receive and sample the outputs of the summer circuits using a clock signal to produce even data bits and odd data bits. First and second multiplexers receive the even data bits and the odd data bits. A first output latch is configured to receive an output of the first multiplexer to provide a select signal for the second multiplexer and to drive the dynamic feedback signal to an even half summer circuit of the summer circuits. A second output latch is configured to receive an output of the second multiplexer to provide a select signal for the first multiplexer and to drive the dynamic feedback signal to an odd half summer circuit of the summer circuits.

    摘要翻译： 判决反馈均衡器（DFE）和方法包括加法电路，用于向接收的输入添加表示h2抽头的动态反馈信号，并推测在h1分接头上。 数据限幅器使用时钟信号接收和采样加法电路的输出，以产生偶数据位和奇数数据位。 第一和第二多路复用器接收偶数据位和奇数数据位。 第一输出锁存器被配置为接收第一多路复用器的输出以提供用于第二多路复用器的选择信号，并且将动态反馈信号驱动到夏季电路的偶数半夏季电路。 第二输出锁存器被配置为接收第二多路复用器的输出以提供用于第一多路复用器的选择信号，并且将动态反馈信号驱动到夏季电路的奇数半夏季电路。