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公开(公告)号：US4722075A
公开(公告)日：1988-01-26
申请号：US786991
申请日：1985-10-15
摘要： An array of transistor memory cells of a type in which each cell has a transistor, a ground select switch and a sense amplifier coupling switch. A bias voltage line on which there is established a voltage V.sub.BIAS is coupled to each bit line by a bit line transistor whose gate during a read mode is at least about a voltage V.sub.T above V.sub.BIAS. Similarly, the source of each transistor is coupled to the bias voltage line by a source line transistor whose gate is more than about a voltage V.sub.T about V.sub.BIAS. The foregoing arrangement ensures that for every non-selected transistor that transistor's source voltage will be equal to its drain voltage so that all non-selected transistors will be substantially non-conducting.
摘要翻译： 一种晶体管存储单元的阵列，其中每个单元具有晶体管，接地选择开关和读出放大器耦合开关。 建立电压VBIAS的偏置电压线通过位线晶体管耦合到每个位线，位线晶体管在读取模式期间的栅极至少约为高于VBIAS的电压VT。 类似地，每个晶体管的源极通过其栅极大约约VBIAS的电压VT的源极线晶体管耦合到偏置电压线。 上述布置确保了对于每个未选择的晶体管，晶体管的源极电压将等于其漏极电压，使得所有未选择的晶体管将基本上不导通。
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公开(公告)号：US4740925A
公开(公告)日：1988-04-26
申请号：US786992
申请日：1985-10-15
CPC分类号： G11C29/24
摘要： A method of making an array of programmable read only semiconductor memory cells which includes forming an extra row of the memory cells and a corresponding extra row gate coupled thereto. Extra row gate enabling means is coupled to the extra row gate for enabling the extra row gate in response to a control signal KILLT applied thereto. A disabling means is coupled to a first selected row gate other than the extra row gate in order to disable the selected row gate in response to a control signal KILLT applied thereto. A disabling means is coupled to a first selected row gate other than the extra row gate in order to disable the selected row gate in response to the control signal KILLT being applied thereto.An NAND gate may be formed with the extra row gate to allow a second set of signals corresponding to a second selected row of memory cells to enable the second selected row gate. A disabling means is coupled to the second selected row gate other than the extra row gate. In response to a control signal KILLB being applied to both the NAND gate and to the gate of the second selected row, it is possible to use the second selected row to test the first selected row and vice versa.
摘要翻译： 一种制造可编程只读半导体存储器单元的阵列的方法，其包括形成存储器单元的额外行和耦合到其上的对应的额外行栅。 额外的行栅极使能装置被耦合到额外的行栅极，以响应于施加到其上的控制信号KILLT来启用额外的行栅极。 禁用装置耦合到除额外行门以外的第一选定行门，以便响应于施加到其上的控制信号KILLT来禁用所选择的行门。 禁止装置耦合到除了额外行门以外的第一选择的行门，以便响应于施加到其上的控制信号KILL而禁用所选择的行门。 NAND门可以用额外的行门形成，以允许对应于第二选定行的存储器单元的第二组信号使第二选择的行门能够被执行。 禁用装置耦合到除了额外的行门之外的第二选择的行门。 响应于控制信号KILLB被施加到NAND门和第二选择行的栅极，可以使用第二选定行来测试第一选定行，反之亦然。
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公开(公告)号：US4797857A
公开(公告)日：1989-01-10
申请号：US850636
申请日：1986-04-11
摘要： A discharge circuit for discharging bit lines of an array of semiconductor memory cells in which the array of bit lines are biased from a single bias line. The discharge circuit includes a discharge switch coupled to the bias line for discharging the bit lines and the bias line and a control circuit coupled to the discharge switch operative to turn on the discharge switch in response to the voltage on the bias line rising above a first predetermined level and then to turn off the discharge switch in response to the voltage on the bias line falling below a second predetermined level.
摘要翻译： 一种放电电路，用于对其中位线阵列从单个偏置线偏置的半导体存储器单元阵列的位线进行放电。 放电电路包括耦合到偏置线用于对位线和偏置线进行放电的放电开关，以及耦合到放电开关的控制电路，用于响应于偏置线上的电压升高到高于第一 然后响应于偏压线上的电压下降到第二预定水平以关闭放电开关。
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4.发明授权Reference circuit for integrated memory arrays having virtual ground connections 失效具有虚拟接地连接的集成存储器阵列的参考电路
公开(公告)号：US4868790A
公开(公告)日：1989-09-19
申请号：US187134
申请日：1988-04-28
IPC分类号： G11C16/28
CPC分类号： G11C16/28
摘要： A reference-column circuit for supplying a reference voltage to be used in sensing programming status of read-only-memory cells in a memory array having virtual-ground circuit connections is disclosed. The reference-column circuit includes an adjacent non-programmed memory cell having a common terminal with an identical non-programmed memory cell of prior-art circuitry. The additional memory cell and associated grounding circuit provide a compensating component of reference voltage to the input of a sense amplifier, the compensating component acting to eliminate a source of possible errors in sense amplifier transmission caused by non-programmed adjacent memory cells in the memory array.
摘要翻译： 公开了一种用于提供用于感测具有虚拟接地电路连接的存储器阵列中的只读存储器单元的编程状态中使用的参考电压的参考列电路。 参考列电路包括具有与现有技术电路相同的非编程存储器单元的公共端子的相邻非编程存储器单元。 附加存储器单元和相关联的接地电路为读出放大器的输入提供参考电压的补偿分量，补偿组件用于消除由存储器阵列中的非编程相邻存储器单元引起的读出放大器传输中的可能误差源 。
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5.发明授权
公开(公告)号：US5399923A
公开(公告)日：1995-03-21
申请号：US96324
申请日：1993-07-26
IPC分类号： H03K19/177 , H01H37/76
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17728 , H03K19/1778
摘要： A field programmable gate array (10) having a plurality of logic modules (31-35) has a pair of driver circuits (51-52) connected between each logic module (31) and logic module interconnection tracks or lines (12-16, 20-23) (51-52). Each of the drivers (51-52) has an input connected to receive a common output signal from the associated logic module (31). The output from each of the driver circuits (51-52) is selectively connectable to one of the interconnection tracks by a different respective antifuse (27). The output of each driver circuit (51-52) has a current magnitude less than a level that would damage the antifuse (27) but greater than a predetermined level, so that the track capacitances can be charged as rapidly as possible to increase the propagation time of a signal in the array. In one embodiment (10), the respective logic module interconnection lines or tracks 12 to which the pair of antifuses are connected are different logic module interconnection lines (12, 13). In another embodiment (150), the respective logic module interconnection lines to which the pair of antifuses (185, 186) are connected are the same logic module interconnection line or track (186).
摘要翻译： 具有多个逻辑模块（31-35）的现场可编程门阵列（10）具有连接在每个逻辑模块（31）和逻辑模块互连磁道或线路（12-16）之间的一对驱动电路（51-52） 20-23）（51-52）。 每个驱动器（51-52）具有连接的输入端以接收来自相关逻辑模块（31）的公共输出信号。 来自每个驱动电路（51-52）的输出可通过不同的相应的反熔丝（27）选择性地连接到一个互连磁道。 每个驱动器电路（51-52）的输出具有小于将损坏反熔丝（27）但大于预定电平的电平的电流幅值，使得轨道电容可以尽可能快地充电以增加传播 阵列中的信号时间。 在一个实施例（10）中，与逻辑模块互连线（12,13）不同的相应的逻辑模块互连线路或一对反熔丝对应的轨道12。 在另一实施例（150）中，连接一对反熔丝（185,186）的相应的逻辑模块互连线是相同的逻辑模块互连线或轨道（186）。
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公开(公告)号：US5485105A
公开(公告)日：1996-01-16
申请号：US283469
申请日：1994-08-01
申请人： Mark G. Harward , David D. Wilmoth
发明人： Mark G. Harward , David D. Wilmoth
CPC分类号： G11C29/027 , G11C17/18 , G11C29/02 , G11C29/028 , G11C29/24 , G11C29/50 , G11C29/50012 , G11C29/52 , G06F2201/81 , G11C2029/5006
摘要： The described embodiments of the present invention provide an apparatus and method for rapidly programming field programmable devices. A dummy antifuse is provided on the field programmable device for testing prior to actual programming. The current drawn by the device is measured by the programming apparatus until an adequate soaking current is measured while programming the test antifuse. The programming apparatus then records the time required this current level and selects that time as the programming period T.sub.p. This programming time T.sub.p is then used to program the entire device. T.sub.p is now the minimum time required given the process variations of this particular device to adequately program the antifuses which must be blown.
摘要翻译： 本发明的所描述的实施例提供了用于快速编程现场可编程设备的装置和方法。 在现场可编程设备上提供虚拟反熔丝，以便在实际编程之前进行测试。 由编程设备测量由设备汲取的电流，直到在对测试反熔丝进行编程时测量足够的均热电流。 然后，编程装置记录所需的该当前电平所需的时间，并选择该时间作为编程周期Tp。 然后，该编程时间Tp用于对整个设备进行编程。 Tp现在是这个特定设备的过程变化所需的最短时间，以便充分地编程必须吹制的反熔丝。
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公开(公告)号：US4963765A
公开(公告)日：1990-10-16
申请号：US376920
申请日：1989-07-03
IPC分类号： H03K5/1534
CPC分类号： H03K5/1534
摘要： A high speed circuit for detecting input or address transitions at a terminal of an integrated circuit logic array. The circuit utilizes N-channel leaker transistors to control the widths of and P-channel transistors to control the risetimes of output pulses and utilizes inverters and OR circuits to sense input or address transitions of both polarities.
摘要翻译： 用于检测集成电路逻辑阵列的端子处的输入或地址转换的高速电路。 该电路利用N沟道漏电晶体管来控制P沟道晶体管的宽度以控制输出脉冲的时间，并利用反相器和OR电路来检测两极的输入或地址转换。
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公开(公告)号：US5488317A
公开(公告)日：1996-01-30
申请号：US141339
申请日：1993-10-22
IPC分类号： H03K19/0185 , H03K19/177 , H03K19/088 , H03K19/094
CPC分类号： H03K19/17788 , H03K19/018585 , H03K19/17704
摘要： An FPGA having a plurality of logic modules with configurable output drivers (8) to enable outputs (y) of several logic modules to be wired together. The output driver (8) comprises a n-channel and a p-channel driver transistor (16, 20) which are connected to a signal (I/O) when no wired outputs (y) are desired. If two or more outputs (y) are to be connected to enable a wired logic function, p-channel transistor (16) is disabled. Then, a weak pull-up transistor (18) may be provided. Alternatively, a senseamp may be provided to the connected outputs (y).
摘要翻译： 具有多个具有可配置输出驱动器（8）的逻辑模块的FPGA，以使多个逻辑模块的输出（y）能够连接在一起。 输出驱动器（8）包括在不需要有线输出（y）时连接到信号（I / O）的n沟道和p沟道驱动晶体管（16,20）。 如果要连接两个或更多个输出（y）以启用有线逻辑功能，则禁用p沟道晶体管（16）。 然后，可以提供弱上拉晶体管（18）。 或者，可以向连接的输出（y）提供感测器。
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9.发明授权Method of making a high-speed 2-transistor cell for programmable/EEPROM devices with separate read and write transistors 失效制造具有独立读和写晶体管的可编程/ EEPROM器件的高速2晶体管单元的方法
公开(公告)号：US5045489A
公开(公告)日：1991-09-03
申请号：US374372
申请日：1989-06-30
申请人： Manzur Gill , David D. Wilmoth
发明人： Manzur Gill , David D. Wilmoth
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521
摘要： A 2-transistor cell (26) comprises buried diffused regions (34, 36 and 38) aligned substantially parallel. Floating gates (40) are aligned substantially perpendicular to the diffused regions (34, 36 and 38). A control gate (42) defines a first channel region between first and second diffused regions (34 and 36) to define a read transistor (30) and a second channel region between second and third diffused regions (36 and 38) to define a program transistor. The read transistor (30) and program transistor (32) may be individually optimized according to their respective functions. Further, tunnel windows (70) may be provided for Fowler-Nordheim tunneling.
摘要翻译： 2晶体管单元（26）包括基本上平行排列的掩埋扩散区域（34,36和38）。 浮动门（40）基本上垂直于扩散区域（34,36和38）排列。 控制栅极（42）限定第一和第二扩散区域（34和36）之间的第一沟道区域，以限定读取晶体管（30）和第二和第三扩散区域（36和38）之间的第二沟道区域，以限定程序 晶体管。 读取晶体管（30）和程序晶体管（32）可根据各自的功能单独优化。 此外，可以为Fowler-Nordheim隧道提供隧道窗口（70）。
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公开(公告)号：US5243490A
公开(公告)日：1993-09-07
申请号：US950763
申请日：1992-09-24
申请人： George S. Ontko , David D. Wilmoth
发明人： George S. Ontko , David D. Wilmoth
CPC分类号： G11C5/005 , G11C16/225
摘要： A FAMOS memory bit (40) is protected from voltage spike caused by an electrostatic discharge or otherwise by an ESD protection circuit (12). Responsive to a voltage spike on V.sub.pp, the ESD protection circuit (12) couples the drain of the FAMOS memory bit (40) to V.sub.cc or another high capacitance node.
摘要翻译： FAMOS存储器位（40）被防止由静电放电引起的电压尖峰或由ESD保护电路（12）引起的电压尖峰。 响应于Vpp上的电压尖峰，ESD保护电路（12）将FAMOS存储器位（40）的漏极耦合到Vcc或另一高电容节点。
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