公开(公告)号：US20090241332A1

公开(公告)日：2009-10-01

申请号：US12078206

申请日：2008-03-28

申请人： John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  James P. Paoletti ,  Kostas I. Papathomas ,  Rajinder S. Rai

发明人： John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  James P. Paoletti ,  Kostas I. Papathomas ,  Rajinder S. Rai

IPC分类号： H05K3/00

CPC分类号： H05K3/462 ,  H05K3/0032 ,  H05K3/4069 ,  H05K3/4623 ,  H05K2201/09318 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/061 ,  Y10T29/49124

摘要： A circuitized substrate and method of making same in which a first plurality of holes are formed within two bonded dielectric layers and then made conductive, e.g., plated. The substrate also includes third and fourth dielectric layers bonded to the first and second with a plurality of continuous electrically conductive thru holes extending through all four dielectric layers. Conductive paste is positioned within the thru holes for providing electrical connections between desired conductive layers of the substrate and outer layers as well. A circuitized substrate assembly and method of making same are also provided.

摘要翻译： 电路化基板及其制造方法，其中第一多个孔形成在两个接合的介电层内，然后导电，例如电镀。 衬底还包括通过延伸穿过所有四个电介质层的多个连续导电通孔与第一和第二电极结合的第三和第四电介质层。 导电浆料位于通孔内，用于在基板和外层的期望的导电层之间提供电连接。 还提供了电路化基板组件及其制造方法。

公开(公告)号：US06593534B2

公开(公告)日：2003-07-15

申请号：US09812261

申请日：2001-03-19

申请人： Gerald W. Jones ,  John M. Lauffer ,  Voya R. Markovich ,  Thomas R. Miller ,  James P. Paoletti ,  Konstantinos I. Papathomas ,  James R. Stack

发明人： Gerald W. Jones ,  John M. Lauffer ,  Voya R. Markovich ,  Thomas R. Miller ,  James P. Paoletti ,  Konstantinos I. Papathomas ,  James R. Stack

IPC分类号： H01R909

CPC分类号： H05K3/462 ,  H05K1/115 ,  H05K3/4069 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0554

摘要： A structure of and method for producing a multilayer printed or wiring circuit board, and more particularly a method producing so-called z-axis or multilayer electrical interconnections in a hierarchial wiring structure in order to be able to provide for an increase in the number of inputs and outputs (I/O) in comparison with a standard printed wiring board (PWB) arrangement, and a printed wiring board produced by the method.