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1.发明申请公开(公告)号：US20110243154A1
公开(公告)日：2011-10-06
申请号：US12749812
申请日：2010-03-30
CPC分类号： H04L1/0079 , H03M13/09 , H04L1/0072
摘要： A method and circuit for implementing variable length packets to embed extra control information in an interconnect system, and a design structure on which the subject circuit resides are provided. Packets are defined to include an End-to-End (ETE) Flow Unit within packet (Flit) count field in the packet header. The packet header also includes its own CRC field. When a nonzero ETE flit count field is received in an incoming packet from an incoming link, the specified number of embedded ETE flits is removed from the packet and is used the same as if the control information arrived in its own packet.
摘要翻译： 一种用于实现可变长度分组以在互连系统中嵌入额外控制信息的方法和电路，以及提供了主题电路所在的设计结构。 分组被定义为在分组报头中的分组（Flit）计数字段内包括端到端（ETE）流单元。 分组报头还包括其自己的CRC字段。 当在来自传入链路的传入分组中接收到非零的ETE飞行计数字段时，从分组中删除指定数量的嵌入式ETE飞行，并且与控制信息到达自己的分组一样被使用。
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2.发明授权Implementing ordered and reliable transfer of packets while spraying packets over multiple links 失效在多个链路上分发数据包时，实现有序可靠的数据包传输公开(公告)号：US08358658B2
公开(公告)日：2013-01-22
申请号：US12727545
申请日：2010-03-19
IPC分类号： H04L12/28
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： A method and circuit for implementing ordered and reliable transfer of packets while spraying packets over multiple links, and a design structure on which the subject circuit resides are provided. Each source interconnect chip maintains a spray mask including multiple available links for each destination chip for spraying packets across multiple links of a local rack interconnect system. Each packet is assigned an End-to-End (ETE) sequence number in the source interconnect chip that represents the packet position in an ordered packet stream from the source device. The destination interconnect chip uses the ETE sequence numbers to reorder the received sprayed packets into the correct order before sending the packets to the destination device.
摘要翻译： 一种用于在通过多个链路喷射分组时实现分组的有序和可靠传送的方法和电路，并且提供了主题电路所在的设计结构。 每个源互连芯片保持喷射掩模，其包括用于每个目的地芯片的多个可用链路，用于在本地机架互连系统的多个链路上喷射分组。 每个数据包被分配在源互连芯片中的端到端（ETE）序列号，其表示来自源设备的有序分组流中的分组位置。 目的互连芯片在将数据包发送到目标设备之前，使用ETE序列号将接收到的喷射数据包重新排序为正确的顺序。
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3.发明授权公开(公告)号：US08514885B2
公开(公告)日：2013-08-20
申请号：US12749812
申请日：2010-03-30
CPC分类号： H04L1/0079 , H03M13/09 , H04L1/0072
摘要： A method and circuit for implementing variable length packets to embed extra control information in an interconnect system, and a design structure on which the subject circuit resides are provided. Packets are defined to include an End-to-End (ETE) Flow Unit within packet (Flit) count field in the packet header. The packet header also includes its own CRC field. When a nonzero ETE flit count field is received in an incoming packet from an incoming link, the specified number of embedded ETE flits is removed from the packet and is used the same as if the control information arrived in its own packet.
摘要翻译： 一种用于实现可变长度分组以在互连系统中嵌入额外控制信息的方法和电路，以及提供了主题电路所在的设计结构。 分组被定义为在分组报头中的分组（Flit）计数字段内包括端到端（ETE）流单元。 分组报头还包括其自己的CRC字段。 当在来自传入链路的传入分组中接收到非零的ETE飞行计数字段时，从分组中删除指定数量的嵌入式ETE飞行，并且与控制信息到达自己的分组一样被使用。
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4.发明申请IMPLEMENTING ORDERED AND RELIABLE TRANSFER OF PACKETS WHILE SPRAYING PACKETS OVER MULTIPLE LINKS 失效在多个链接上分发包装时执行包装的可靠转让公开(公告)号：US20110228783A1
公开(公告)日：2011-09-22
申请号：US12727545
申请日：2010-03-19
IPC分类号： H04L12/56
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： A method and circuit for implementing ordered and reliable transfer of packets while spraying packets over multiple links, and a design structure on which the subject circuit resides are provided. Each source interconnect chip maintains a spray mask including multiple available links for each destination chip for spraying packets across multiple links of a local rack interconnect system. Each packet is assigned an End-to-End (ETE) sequence number in the source interconnect chip that represents the packet position in an ordered packet stream from the source device. The destination interconnect chip uses the ETE sequence numbers to reorder the received sprayed packets into the correct order before sending the packets to the destination device.
摘要翻译： 一种用于在通过多个链路喷射分组时实现分组的有序和可靠传送的方法和电路，并且提供了主题电路所在的设计结构。 每个源互连芯片保持喷射掩模，其包括用于每个目的地芯片的多个可用链路，用于在本地机架互连系统的多个链路上喷射分组。 每个数据包被分配在源互连芯片中的端到端（ETE）序列号，其表示来自源设备的有序分组流中的分组位置。 目的互连芯片在将数据包发送到目标设备之前，使用ETE序列号将接收到的喷射数据包重新排序为正确的顺序。
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公开(公告)号：US08416785B2
公开(公告)日：2013-04-09
申请号：US12764193
申请日：2010-04-21
IPC分类号： H04L12/28
CPC分类号： H04L47/34 , H04L45/245 , H04L49/552
摘要： A method and circuit for implementing multiple active paths between source and destination devices in an interconnect system while removing ghost packets, and a design structure on which the subject circuit resides are provided. Each packet includes a generation ID and is assigned an End-to-End (ETE) sequence number in the source interconnect chip that represents the packet position in an ordered packet stream from the source device. The packets are transmitted from a source interconnect chip source to a destination interconnect chip on the multiple active paths. The generation ID of a received packet is compared with a current generation ID at a destination interconnect chip to validate packet acceptance. The destination interconnect chip uses the ETE sequence numbers to reorder the accepted received packets into the correct order before sending the packets to the destination device.
摘要翻译： 一种用于在去除重影分组的同时在互连系统中实现源和目的设备之间的多个活动路径的方法和电路，以及提供了所述主题电路所在的设计结构。 每个分组包括生成ID，并且在源互连芯片中分配表示来自源设备的有序分组流中的分组位置的端到端（ETE）序列号。 分组从源互连芯片源传输到多个主动路径上的目的地互连芯片。 将接收到的分组的生成ID与目的地互连芯片上的当前生成ID进行比较，以验证分组接受。 目的互连芯片在将数据包发送到目标设备之前，使用ETE序列号将接收的接收数据包重新排序为正确的顺序。
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公开(公告)号：US08340112B2
公开(公告)日：2012-12-25
申请号：US12731715
申请日：2010-03-25
IPC分类号： H04L12/54
CPC分类号： G06F13/4022 , H04L49/1523 , H04L49/251 , H04L49/252
摘要： A method and circuit for implementing enhanced link bandwidth for a headless interconnect chip in a local rack interconnect system, and a design structure on which the subject circuit resides are provided. The headless interconnect chip includes a cut through switch and a store and forward switch. A packet is received from an incoming link to be transmitted on an outgoing link on the headless interconnect chip. Both the cut through switch and the store and forward switch are selectively used for moving packets received from the incoming link to the outgoing link on the headless interconnect chip.
摘要翻译： 一种用于实现本地机架互连系统中的无头互连芯片的增强的链路带宽的方法和电路，以及提供了所述主题电路所在的设计结构。 无头互连芯片包括切断开关和存储和正向开关。 从在无头互连芯片上的输出链路上传送的传入链路接收分组。 切断开关和存储和正向开关都有选择地用于将从进入链路接收的分组移动到无头互连芯片上的输出链路。
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公开(公告)号：US20110261821A1
公开(公告)日：2011-10-27
申请号：US12764193
申请日：2010-04-21
IPC分类号： H04L12/56
CPC分类号： H04L47/34 , H04L45/245 , H04L49/552
摘要： A method and circuit for implementing multiple active paths between source and destination devices in an interconnect system while removing ghost packets, and a design structure on which the subject circuit resides are provided. Each packet includes a generation ID and is assigned an End-to-End (ETE) sequence number in the source interconnect chip that represents the packet position in an ordered packet stream from the source device. The packets are transmitted from a source interconnect chip source to a destination interconnect chip on the multiple active paths. The generation ID of a received packet is compared with a current generation ID at a destination interconnect chip to validate packet acceptance. The destination interconnect chip uses the ETE sequence numbers to reorder the accepted received packets into the correct order before sending the packets to the destination device.
摘要翻译： 一种用于在去除重影分组的同时在互连系统中的源和目的设备之间实现多个活动路径的方法和电路，以及提供了所述主题电路所在的设计结构。 每个分组包括生成ID，并且在源互连芯片中分配表示来自源设备的有序分组流中的分组位置的端到端（ETE）序列号。 分组从源互连芯片源传输到多个主动路径上的目的地互连芯片。 将接收到的分组的生成ID与目的地互连芯片上的当前生成ID进行比较，以验证分组接受。 目的互连芯片在将数据包发送到目标设备之前，使用ETE序列号将接收的接收数据包重新排序为正确的顺序。
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公开(公告)号：US20110235652A1
公开(公告)日：2011-09-29
申请号：US12731715
申请日：2010-03-25
CPC分类号： G06F13/4022 , H04L49/1523 , H04L49/251 , H04L49/252
摘要： A method and circuit for implementing enhanced link bandwidth for a headless interconnect chip in a local rack interconnect system, and a design structure on which the subject circuit resides are provided. The headless interconnect chip includes a cut through switch and a store and forward switch. A packet is received from an incoming link to be transmitted on an outgoing link on the headless interconnect chip. Both the cut through switch and the store and forward switch are selectively used for moving packets received from the incoming link to the outgoing link on the headless interconnect chip.
摘要翻译： 一种用于实现本地机架互连系统中的无头互连芯片的增强的链路带宽的方法和电路，以及提供了所述主题电路所在的设计结构。 无头互连芯片包括切断开关和存储和正向开关。 从在无头互连芯片上的输出链路上传送的传入链路接收分组。 切断开关和存储和正向开关都有选择地用于将从进入链路接收的分组移动到无头互连芯片上的输出链路。
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9.发明授权公开(公告)号：US08010682B2
公开(公告)日：2011-08-30
申请号：US11023706
申请日：2004-12-28
CPC分类号： G06F12/0817 , G06F2212/507
摘要： In a shared memory architecture, early coherency indication is used to notify a communications interface, prior to the data for a memory request is returned, and prior to updating a coherency directory in response to the memory request, that the return data can be used by the communications interface when it is received thereby from a source of the return data. By doing so, the communications interface can often begin forwarding the return data over its associated communication link with little or no latency once the data is retrieved from its source. In addition, the communications interface is often no longer required to wait for updating of the coherency directory to complete prior to forwarding the return data over the communication link. As such, the overall latency for handling the memory request is typically reduced.
摘要翻译： 在共享存储器架构中，早期一致性指示用于在返回存储器请求的数据之前以及在响应于存储器请求更新一致性目录之前通知通信接口，返回数据可以由 当从返回数据的来源接收通信接口时。 通过这样做，一旦数据从其源中检索，通信接口通常可以在几乎没有或没有延迟的情况下开始转发其相关联的通信链路上的返回数据。 此外，通常不需要通信接口在通过通信链路转发返回数据之前等待更新相干性目录来完成。 因此，处理存储器请求的总体延迟通常减少。
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10.发明授权Circuit arrangement and method incorporating data buffer with priority-based data storage 失效具有基于优先级的数据存储的数据缓冲器的电路布置和方法公开(公告)号：US06260090B1
公开(公告)日：2001-07-10
申请号：US09262158
申请日：1999-03-03
IPC分类号： G06F1300
CPC分类号： G06F13/18
摘要： A data processing system, circuit arrangement, integrated circuit device, program product, and method utilize a data buffer with a priority-based data storage capability to handle incoming data from a plurality of available data sources. With such a capability, different relative priority levels are assigned to data associated with different data sources. Such priority levels are then used by control logic coupled to the buffer to control whether or not incoming data is stored (or optionally discarded) in the buffer. In particular, the relative priority of incoming data is compared with that associated with data currently stored in the buffer, with the incoming data being stored in the buffer only when its relative priority exceeds that of the currently-stored data.
摘要翻译： 数据处理系统，电路装置，集成电路装置，程序产品和方法利用具有基于优先级的数据存储能力的数据缓冲器来处理来自多个可用数据源的输入数据。 利用这样的能力，将不同的相对优先级分配给与不同数据源相关联的数据。 这样的优先级然后被耦合到缓冲器的控制逻辑使用，以控制是否在缓冲器中存储（或可选地丢弃）输入数据。 特别地，将输入数据的相对优先级与与当前存储在缓冲器中的数据相关联的输入数据的相对优先级进行比较，其中输入数据仅在其相对优先级超过当前存储的数据的情况下存储在缓冲器中。
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