利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

13 条记录 (耗时 0.026 秒)

    Computer with optimizing hardware for conditional hedge fetching into cache storage
    1.
    发明授权
    Computer with optimizing hardware for conditional hedge fetching into cache storage 失效
    具有优化硬件的计算机，用于将条件对冲提取到高速缓存存储中

    公开(公告)号：US6035392A

    公开(公告)日：2000-03-07

    申请号：US26923

    申请日：1998-02-20

    申请人： John Stephen Liptay ,  Mark Anthony Check ,  Barry Watson Krumm ,  Jennifer Almoradie Navarro ,  Charles Franklin Webb

    发明人： John Stephen Liptay ,  Mark Anthony Check ,  Barry Watson Krumm ,  Jennifer Almoradie Navarro ,  Charles Franklin Webb

    IPC分类号： G06F9/38 ,  G06F9/00

    CPC分类号： G06F9/3804

    摘要： A computer for executing programs and having a structure for fetching instructions and/or operands along a path which may not be taken by a process being executed by a computer processor having a hierarchical memory structure with data being loaded into cache lines of a cache in the structure, and having block line fetch signal selection logic and computational logic with hedge selection logic for generating line fetch block signals for control of hedging by fetching instructions and/or operands along a path which may not be taken by a process being executed and making selected hedge fetches sensitive to whether the data is in the cache so as to gain the best performance advantage with a selected hedge fetch signal which accompanies each fetch request to the cache to identify whether a line should be loaded if it misses the cache to indicate a selected hedge fetch when this signal is ON, and rejecting a fetch request in the event the selected hedge fetch signal is turned ON if the data is not in the cache, the cache will reject the fetch, and thereafter repeating the fetch request after a fetch request has been rejected when the selected hedge fetch signal was turned ON the data was not in the cache to repeat the fetch request at a later time when it is more certain that the process being executed wants the data, or never repeating the request upon determination that the process being executed does not need the data to he fetched.

    摘要翻译： 一种用于执行程序并具有用于沿着路径获取指令和/或操作数的结构的计算机，该路径可能不被由具有分层存储器结构的计算机处理器执行的进程执行，其中数据被加载到高速缓存的高速缓存行中 结构，并且具有块线取指信号选择逻辑和具有对冲选择逻辑的计算逻辑，用于产生线取指块信号，用于通过沿着路径获取指令和/或操作数来控制对冲，所述路径可能不被被执行的进程采取并且被选择 对冲提取对数据是否在高速缓存中敏感，以便通过选择的对冲提取信号获得最佳的性能优势，该信号伴随着每个提取请求到高速缓存，以识别是否应该加载行，如果它错过高速缓存以指示所选择的 当该信号为ON时，进行套期提取，并且如果所选择的对冲获取信号为ON，则拒绝提取请求 高速缓存不在缓存中，则缓存将拒绝该提取，并且此后在所选择的对冲提取信号被接通时，在拒绝提取请求之后重复该提取请求，该数据不在高速缓存中以在稍后重复该提取请求 更确定正在执行的进程想要数据的时间，或者在确定正在执行的进程不需要他获取的数据的情况下，永远不会重复该请求。

    Method for conditional hedge fetching into cache storage
    2.
    发明授权
    Method for conditional hedge fetching into cache storage 失效
    用于条件对冲取入缓存存储的方法

    公开(公告)号：US6026488A

    公开(公告)日：2000-02-15

    申请号：US27153

    申请日：1998-02-20

    申请人： John Stephen Liptay ,  Mark Anthony Check ,  Barry Watson Krumm ,  Jennifer Almoradie Navarro ,  Charles Franklin Webb

    发明人： John Stephen Liptay ,  Mark Anthony Check ,  Barry Watson Krumm ,  Jennifer Almoradie Navarro ,  Charles Franklin Webb

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3804

    摘要： A computer for executing programs and having a structure for fetching instructions and/or operands along a path which may not be taken by a process being executed by a computer processor having a hierarchical memory structure with data being loaded into cache lines of a cache in the structure, and having block line fetch signal selection logic and computational logic with hedge selection logic for generating line fetch block signals for control of hedging by fetching instructions and/or operands along a path which may not be taken by a process being executed and making selected hedge fetches sensitive to whether the data is in the cache so as to gain the best performance advantage with a selected hedge fetch signal which accompanies each fetch request to the cache to identify whether a line should be loaded if it misses the cache to indicate a selected hedge fetch when this signal is ON, and rejecting a fetch request in the event the selected hedge fetch signal is turned ON if the data is not in the cache, the cache will reject the fetch, and thereafter repeating the fetch request after a fetch request has been rejected when the the selected hedge fetch signal was turned ON the data was not in the cache to repeat the fetch request at a later time when it is more certain that the process being executed wants the data, or never repeating the request upon determination that the process being executed does not need the data to be fetched.

    摘要翻译： 一种用于执行程序并具有用于沿着路径获取指令和/或操作数的结构的计算机，该路径可能不被由具有分层存储器结构的计算机处理器执行的进程执行，其中数据被加载到高速缓存的高速缓存行中 结构，并且具有块线取指信号选择逻辑和具有对冲选择逻辑的计算逻辑，用于产生线取指块信号，用于通过沿着路径获取指令和/或操作数来控制对冲，所述路径可能不被被执行的进程采取并且被选择 对冲提取对数据是否在高速缓存中敏感，以便通过选择的对冲提取信号获得最佳的性能优势，该信号伴随着每个提取请求到高速缓存，以识别是否应该加载行，如果它错过高速缓存以指示所选择的 当该信号为ON时，进行套期提取，并且如果所选择的对冲获取信号为ON，则拒绝提取请求 高速缓存不在缓存中，则缓存将拒绝该提取，并且此后在所选择的对冲提取信号被接通时，在拒绝提取请求之后重复获取请求，否则数据不在高速缓存中，以在一个 稍后时间，当确定正在执行的进程想要数据时，或者在确定正在执行的进程不需要要获取的数据的情况下从不重复该请求。

    Computer processor system for executing RXE format floating point instructions
    5.
    发明授权
    Computer processor system for executing RXE format floating point instructions 失效
    用于执行RXE格式浮点指令的计算机处理器系统

    公开(公告)号：US6085313A

    公开(公告)日：2000-07-04

    申请号：US070198

    申请日：1998-04-30

    申请人： Mark Anthony Check ,  Ronald M. Smith, Sr. ,  John Stephen Liptay ,  Eric Mark Schwarz ,  Timothy John Slegel ,  Charles Franklin Webb

    发明人： Mark Anthony Check ,  Ronald M. Smith, Sr. ,  John Stephen Liptay ,  Eric Mark Schwarz ,  Timothy John Slegel ,  Charles Franklin Webb

    IPC分类号： G06F9/355 ,  G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/30145

    摘要： A computer processor system having a floating point processor for instructions which are processed in a six cycle pipeline, in which prior to the first cycle of the pipeline an instruction text is fetched, and during the first cycle for the fetched particular instruction it is decoded and the base (B) and index (X) register values are read for use in address generation. Instructions of the RX-type are extended by placing the extension of the operation code beyond the first four bytes of the instruction format and to assign the operation codes in such a way that the machine may determine from the first 8 bits of the operation code alone, the exact format of the instruction. Instructions formats include the ESA/390 instructions SS, RR; RX; S; RRE; RI: and the new RXE instructions. where instructions of the RXE format have their R.sub.1, X.sub.2, B.sub.2, and D.sub.2 fields in the identical positions in said instruction register as in the RX format to enable the processor to determine from the first 8 bits of the operation code alone that an instruction being decoded is an RXE format instruction and the register indexed extensions of the RXE format instruction, after which it gates the correct information to said X-B-D adder. During the second cycle the address add of B+X+Displacement is performed and sent to the cache processor's, and during the third and fourth cycles the cache is respectively accessed and data is returned, and during a fifth cycle execution of the fetched instruction occurs with the result putaway in a sixth cycle.RXE instructions can be used for floating point processing and fixed point processing.

    摘要翻译： 一种计算机处理器系统，具有用于指令的浮点处理器，其在六个周期流水线中被处理，其中在流水线的第一周期之前取出指令文本，并且在所读取的特定指令的第一周期期间对其进行解码， 读取基地址（B）和索引（X）寄存器值以用于地址生成。 通过将操作代码的扩展置于指令格式的前四个字节之外来扩展RX类型的指令，并且以这样的方式分配操作代码，使得机器可以仅从操作代码的前8位确定 ，指令的确切格式。 指令格式包括ESA / 390指令SS，RR; RX; S; RRE; RI：和新的RXE指令。 其中RXE格式的指令在RX格式中在所述指令寄存器中的相同位置具有它们的R1，X2，B2和D2字段，以使处理器仅从操作代码的前8位确定指令为 解码的是RXE格式指令和RXE格式指令的寄存器索引扩展，然后将正确的信息写入所述XBD加法器。 在第二周期期间，执行B + X +位移的地址添加并发送到高速缓存处理器，并且在第三和第四周期期间，分别访问高速缓存并返回数据，并且在第五周期期间执行所提取的指令 结果放在第六个循环中.RXE指令可用于浮点处理和定点处理。

    Millimode capable computer system providing global branch history table disables and separate millicode disables which enable millicode disable to be turned off for some sections of code execution but not disabled for all
    6.
    发明授权
    Millimode capable computer system providing global branch history table disables and separate millicode disables which enable millicode disable to be turned off for some sections of code execution but not disabled for all 失效
    提供全球分支历史表的具有Millimode功能的计算机系统禁用和分离的millicode禁用，这使得可以关闭某些代码段但不对所有的代码执行millicode禁用

    公开(公告)号：US6125444A

    公开(公告)日：2000-09-26

    申请号：US70201

    申请日：1998-04-30

    申请人： Mark Anthony Check ,  John Stephen Liptay ,  Timothy John Slegel ,  Charles Franklin Webb ,  Mark Steven Farrell

    发明人： Mark Anthony Check ,  John Stephen Liptay ,  Timothy John Slegel ,  Charles Franklin Webb ,  Mark Steven Farrell

    IPC分类号： G06F9/22 ,  G06F9/26 ,  G06F9/38

    CPC分类号： G06F9/3844

    摘要： A millimode capable computer system provides control to millicode to allow the BHT operations to continue except when the these special situations occur that require control of instruction fetch operations must be provided and the BHT can be turned off for some sections of code execution, but not disabled for all. A single free running BHT functions for both a normal mode and a millimode for the central processor which can execute in millimode with a branch history table directing instruction fetch for which both a global BHT disable and millicode disables exist. Hit detection logic receives input from the global BHT disable, as well as from an initialized control register bit and a processor control register bit to select the correct set target information and generate a "branch history table hit detected" control signal.

    摘要翻译： 具有毫米级功能的计算机系统提供对millicode的控制以允许BHT操作继续，除非出现这些特殊情况需要提供指令提取操作的控制，并且BHT可以在某些代码执行部分被关闭但不被禁用 对全部。 单个免费运行的BHT功能可用于中央处理器的正常模式和毫模式，可以以毫米模式执行，其中分支历史表指示全局BHT禁用和毫代码禁用两者之间存在禁用指令的指令提取。 命中检测逻辑接收来自全局BHT禁用的输入，以及从初始化的控制寄存器位和处理器控制寄存器位选择正确的设置目标信息并生成“检测到分支历史表命中”控制信号。

    Address bit decoding for same adder circuitry for RXE instruction format with same XBD location as RX format and dis-jointed extended operation code
    7.
    发明授权
    Address bit decoding for same adder circuitry for RXE instruction format with same XBD location as RX format and dis-jointed extended operation code 失效
    地址比特解码用于RXE指令格式的相同加法器电路，具有与RX格式相同的XBD位置和解码的扩展操作码

    公开(公告)号：US6105126A

    公开(公告)日：2000-08-15

    申请号：US70359

    申请日：1998-04-30

    申请人： Mark Anthony Check ,  Ronald M. Smith, Sr. ,  John Stephen Liptay ,  Eric Mark Schwarz ,  Timothy John Slegel ,  Charles Franklin Webb

    发明人： Mark Anthony Check ,  Ronald M. Smith, Sr. ,  John Stephen Liptay ,  Eric Mark Schwarz ,  Timothy John Slegel ,  Charles Franklin Webb

    IPC分类号： G06F9/355 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/34

    CPC分类号： G06F9/355 ,  G06F9/30185

    摘要： A computer processor floating point processor six cycle pipeline system where instruction text is fetched prior to the first cycle and decoded during the first cycle for the fetched particular instruction and the base (B) and index (X) register values are read for use in address generation. RXE Instructions are of the RX-type but extended by placing the extension of the operation code beyond the first four bytes of the instruction format and to assign the operation codes in such a way that the machine may determine the exact format from the first 8 bits of the operation code alone. ESA/390 instructions SS, RR; RX; S; RRE; RI; and the new RXE instructions have a format which can be used for fixed point processing as well as floating point processing where instructions of the RXE format have their R1, X2, B2, and D2 fields in the identical positions in said instruction register as in the RX format to enable the processor to determine from the first 8 bits of the operation code alone that an instruction being decoded is an RXE format instruction and the register indexed extensions of the RXE format instruction, after which it gates the correct information to said X-B-D adder. During the second cycle the address add of B+X+Displacement is performed and sent to the cache processor's, and during the third and fourth cycles the cache is respectively accessed and data is returned, and during a fifth cycle execution of the fetched instruction occurs with the result putaway in a sixth cycle.

    摘要翻译： 计算机处理器浮点处理器六循环流水线系统，其中指令文本在第一周期之前获取并且在第一周期期间被解码用于所提取的特定指令，并且基准（B）和索引（X）寄存器值被读取用于地址 代。 RXE指令是RX型，但通过将操作码的扩展置于指令格式的前四个字节之外进行扩展，并以这样的方式分配操作码，使得机器可以从前8位确定确切的格式 的操作代码。 ESA / 390指令SS，RR; RX; S; RRE; RI; 并且新的RXE指令具有可用于固定点处理以及浮点处理的格式，其中RXE格式的指令在所述指令寄存器中的相同位置具有其R1，X2，B2和D2字段，如 RX格式，使处理器能够从操作代码的前8位确定正在解码的指令是RXE格式指令和RXE格式指令的寄存器索引扩展，之后它将正确信息锁定到所述XBD加法器 。 在第二周期期间，执行B + X +位移的地址添加并发送到高速缓存处理器，并且在第三和第四周期期间，分别访问高速缓存并返回数据，并且在第五周期期间执行所取出的指令 结果放在第六个周期。

    Globally or selectively disabling branch history table operations during sensitive portion of millicode routine in millimode supporting computer
    10.
    发明授权
    Globally or selectively disabling branch history table operations during sensitive portion of millicode routine in millimode supporting computer 失效
    在毫秒支持计算机中的millicode例程的敏感部分，全局或选择性地禁用分支历史表操作

    公开(公告)号：US6108776A

    公开(公告)日：2000-08-22

    申请号：US70362

    申请日：1998-04-30

    申请人： Mark Anthony Check ,  John Stephen Liptay ,  Timothy John Slegel ,  Charles Franklin Webb ,  Mark Steven Farrell

    发明人： Mark Anthony Check ,  John Stephen Liptay ,  Timothy John Slegel ,  Charles Franklin Webb ,  Mark Steven Farrell

    IPC分类号： G06F9/22 ,  G06F9/26 ,  G06F9/318 ,  G06F9/38 ,  G06F9/32

    CPC分类号： G06F9/3806 ,  G06F9/3017

    摘要： A millimode capable computer system provides control to millicode to allow the BHT operations to continue except when the these special situations occur that require control of instruction fetch operations must be provided and the BHT can be turned off for some sections of code execution, but not disabled for all. A single free running BHT functions for both a normal mode and a millimode for the central processor which can execute in millimode with a branch history table directing instruction fetch for which both a global BHT disable and millicode disables exist. Hit detection logic receives input from the global BHT disable, as well as from an initialized control register bit and a processor control register bit to select the correct set target information and generate a "branch history table hit detected" control signal.

    摘要翻译： 具有毫米级功能的计算机系统提供对millicode的控制以允许BHT操作继续，除非出现这些特殊情况需要提供指令提取操作的控制，并且BHT可以在某些代码执行部分被关闭但不被禁用 对全部。 单个免费运行的BHT功能可用于中央处理器的正常模式和毫模式，可以以毫米模式执行，其中分支历史表指示全局BHT禁用和毫代码禁用两者之间存在禁用指令的指令提取。 命中检测逻辑接收来自全局BHT禁用的输入，以及从初始化的控制寄存器位和处理器控制寄存器位选择正确的设置目标信息并生成“检测到分支历史表命中”控制信号。