公开(公告)号：US20050079889A1

公开(公告)日：2005-04-14

申请号：US10682746

申请日：2003-10-09

申请人： John Vaglica ,  Christopher Chun ,  Jose Corleto-Mena ,  Arnaldo Cruz ,  Jianping Tao ,  Mieu Vu ,  Mark Elledge ,  Charbel Khawand ,  Arthur Goldberg ,  David Hayes

发明人： John Vaglica ,  Christopher Chun ,  Jose Corleto-Mena ,  Arnaldo Cruz ,  Jianping Tao ,  Mieu Vu ,  Mark Elledge ,  Charbel Khawand ,  Arthur Goldberg ,  David Hayes

IPC分类号： H04M11/00 ,  H04W84/08 ,  H04B1/38

CPC分类号： H04W84/08

摘要： A cellular mobile station including a modem processor and memory. The memory includes instructions for the modem processor to perform layer 1 processor operations, layer 2 processor operations, and layer 3 processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol. In one example, the mobile station includes different levels of memory to provide different deterministic access times

摘要翻译： 包括调制解调器处理器和存储器的蜂窝移动站。 存储器包括用于调制解调器处理器执行第1层处理器操作，第2层处理器操作和第3层处理器操作的指令。 调制解调器处理器执行指令，以便根据蜂窝通信协议对蜂窝移动站执行通信数据的处理器操作。 在一个示例中，移动站包括不同级别的存储器以提供不同的确定性访问时间

公开(公告)号：US20050080966A1

公开(公告)日：2005-04-14

申请号：US10682558

申请日：2003-10-09

申请人： Arnaldo Cruz ,  John Vaglica ,  William Moyer ,  Tuongvu Nguyen

发明人： Arnaldo Cruz ,  John Vaglica ,  William Moyer ,  Tuongvu Nguyen

IPC分类号： G06F13/14 ,  G06F13/24 ,  G06F13/38

CPC分类号： G06F13/385 ,  G06F13/24 ,  G06F2213/0042

摘要： New approaches for providing communication between multiple masters (12, 14) and one or more shared resources (24, 30, 100) are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard (100). The USB specification defines the use of USB endpoints as data and control channels that reside in a USB device. In some cases it is desirable to have a certain number of endpoints controlled by one processor, and other endpoints controlled by a different processor, thus providing a shared control of all the endpoints. Circuitry (402, 417, 480) may be used to provide steering for additional signals such as interrupts. Other shared resources (24, 30) may use more centralized circuitry (36) to perform a steering function for additional signals.

摘要翻译： 需要用于在多个主机（12,14）和一个或多个共享资源（24,30,100）之间提供通信的新方法。 可能需要共享的资源的一个例子是符合通用串行总线（USB）标准（100）的电路。 USB规范将USB端点定义为位于USB设备中的数据和控制通道。 在一些情况下，期望具有由一个处理器控制的一定数量的端点以及由不同处理器控制的其他端点，从而提供对所有端点的共享控制。 电路（402,417,480）可用于为诸如中断的附加信号提供转向。 其他共享资源（24,30）可以使用更集中的电路（36）来执行附加信号的转向功能。

公开(公告)号：US20070088889A1

公开(公告)日：2007-04-19

申请号：US11610956

申请日：2006-12-14

申请人： Arnaldo Cruz ,  John Vaglica ,  William Moyer ,  Tuongvu Nguyen

发明人： Arnaldo Cruz ,  John Vaglica ,  William Moyer ,  Tuongvu Nguyen

IPC分类号： G06F13/24

CPC分类号： G06F13/385 ,  G06F13/24 ,  G06F2213/0042

摘要： New approaches for providing communication between multiple masters (12, 14) and one or more shared resources (24, 30, 100) are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard (100). The USB specification defines the use of USB endpoints as data and control channels that reside in a USB device. In some cases it is desirable to have a certain number of endpoints controlled by one processor, and other endpoints controlled by a different processor, thus providing a shared control of all the endpoints. Circuitry (402, 417, 480) may be used to provide steering for additional signals such as interrupts. Other shared resources (24, 30) may use more centralized circuitry (36) to perform a steering function for additional signals.

摘要翻译： 需要用于在多个主机（12,14）和一个或多个共享资源（24,30,100）之间提供通信的新方法。 可能需要共享的资源的一个例子是符合通用串行总线（USB）标准（100）的电路。 USB规范将USB端点定义为位于USB设备中的数据和控制通道。 在一些情况下，期望具有由一个处理器控制的一定数量的端点以及由不同处理器控制的其他端点，从而提供对所有端点的共享控制。 电路（402,417,480）可用于为诸如中断的附加信号提供转向。 其他共享资源（24,30）可以使用更集中的电路（36）来执行附加信号的转向功能。

公开(公告)号：US20050080961A1

公开(公告)日：2005-04-14

申请号：US10682571

申请日：2003-10-09

申请人： Ryan Bedwell ,  Arnaldo Cruz ,  John Vaglica ,  William Moyer

发明人： Ryan Bedwell ,  Arnaldo Cruz ,  John Vaglica ,  William Moyer

IPC分类号： G06F20060101 ,  G06F13/36 ,  G06F13/364

CPC分类号： G06F13/364

摘要： New approaches for providing communication between multiple masters (12, 14) and one or more shared resources (24, 30, 100) are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard (100). The USB specification defines the use of USB endpoints as data and control channels that reside in a USB device. In some cases it is desirable to have a certain number of endpoints controlled by one processor, and other endpoints controlled by a different processor, thus providing a shared control of all the endpoints. Circuitry (402, 417, 480) may be used to provide steering for additional signals such as interrupts. Other shared resources (24, 30) may use more centralized circuitry (36) to perform a steering function for additional signals.

公开(公告)号：US20070153606A1

公开(公告)日：2007-07-05

申请号：US11685419

申请日：2007-03-13

申请人： Arnaldo Cruz ,  Qadeer Qureshi

发明人： Arnaldo Cruz ,  Qadeer Qureshi

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40626

摘要： A system for controlling the refresh cycles of a DRAM cell array based upon a temperature measurement. During active mode, a refresh request indication based on a measured temperature is provided to a DRAM controller (e.g. of another integrated circuit die), wherein the DRAM controller initiates a refresh cycle of the DRAM cell array in response thereto. In a self refreshing mode, the DRAM controller does not initiate refresh cycles, but refresh cycles are performed by a controller on the integrated circuit die of the array based upon a temperature measurement.

摘要翻译： 一种用于基于温度测量来控制DRAM单元阵列的刷新周期的系统。 在活动模式期间，将基于测量温度的刷新请求指示提供给DRAM控制器（例如另一个集成电路管芯），其中DRAM控制器响应于此启动DRAM单元阵列的刷新周期。 在自刷新模式下，DRAM控制器不启动刷新周期，但是基于温度测量，由阵列的集成电路管芯上的控制器执行刷新周期。

公开(公告)号：US20060114734A1

公开(公告)日：2006-06-01

申请号：US11000560

申请日：2004-12-01

申请人： Arnaldo Cruz ,  Qadeer Qureshi

发明人： Arnaldo Cruz ,  Qadeer Qureshi

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40626

摘要： A system for controlling the refresh cycles of a DRAM cell array based upon a temperature measurement. During active mode, a refresh request indication based on a measured temperature is provided to a DRAM controller (e.g. of another integrated circuit die), wherein the DRAM controller initiates a refresh cycle of the DRAM cell array in response thereto. In a self refreshing mode, the DRAM controller does not initiate refresh cycles, but refresh cycles are performed by a controller on the integrated circuit die of the array based upon a temperature measurement.

摘要翻译： 一种用于基于温度测量来控制DRAM单元阵列的刷新周期的系统。 在活动模式期间，将基于测量温度的刷新请求指示提供给DRAM控制器（例如另一个集成电路管芯），其中DRAM控制器响应于此启动DRAM单元阵列的刷新周期。 在自刷新模式下，DRAM控制器不启动刷新周期，但是基于温度测量，由阵列的集成电路管芯上的控制器执行刷新周期。

公开(公告)号：US20050102444A1

公开(公告)日：2005-05-12

申请号：US10703924

申请日：2003-11-07

申请人： Arnaldo Cruz

发明人： Arnaldo Cruz

IPC分类号： G06F13/16 ,  G06F13/28

CPC分类号： G06F13/1605 ,  G06F13/1684 ,  Y02D10/14

摘要： One embodiment relates to a memory controller using an independent memory controller bus in order to transfer data between two or more memories. One embodiment of a data processing system includes a system bus, a system bus master coupled to the system bus, a first memory controller for controlling a first memory, a second memory controller for controlling a second memory, and a memory controller bus operating independent of the system bus to transfer data between the first memory controller and the second memory controller. The memory controller bus may include a data bus and read, write, and acknowledge signals. In one embodiment, the first memory is a block accessible memory such as a NAND Flash memory and the second memory is a random access memory (RAM) such as an SDRAM. The second memory may include arbitration logic for arbitrating between the system bus master and the first memory controller.

摘要翻译： 一个实施例涉及使用独立存储器控制器总线的存储器控​​制器，以便在两个或更多个存储器之间传送数据。 数据处理系统的一个实施例包括系统总线，耦合到系统总线的系统总线主机，用于控制第一存储器的第一存储器控制器，用于控制第二存储器的第二存储器控制器，以及独立于 所述系统总线在第一存储器控制器和第二存储器控制器之间传送数据。 存储器控制器总线可以包括数据总线和读取，写入和确认信号。 在一个实施例中，第一存储器是诸如NAND闪存的块可访问存储器，并且第二存储器是诸如SDRAM的随机存取存储器（RAM）。 第二存储器可以包括用于在系统总线主机和第一存储器控制器之间进行仲裁的仲裁逻辑。