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    Data recovery method and apparatus
    4.
    发明授权
    Data recovery method and apparatus 有权
    数据恢复方法和装置

    公开(公告)号：US06907096B1

    公开(公告)日：2005-06-14

    申请号：US09670598

    申请日：2000-09-29

    申请人： Jonathan C. Lueker ,  Dean Warren ,  Kenneth B. Oliver

    发明人： Jonathan C. Lueker ,  Dean Warren ,  Kenneth B. Oliver

    IPC分类号： H04L7/00 ,  H04L7/04

    CPC分类号： H04L7/046

    摘要： In order to recover phase information, data transmitted at a first frequency is over-sampled using a clock at a second frequency, n times per bit time to obtain n samples. The n samples are used to detect the transitions between two logic levels in said transmitted data which are stored in groups of m sets of said n edge results which are, in turn output at a clock frequency which is the second frequency divided by m, for further processing.

    摘要翻译： 为了恢复相位信息，以第一频率发送的数据以第二频率的时钟进行过采样，每比特时间n次，以获得n个采样。 所述n个采样用于检测所述发送数据中的两个逻辑电平之间的转换，这些转换存储在所述n个边沿结果的m个组的组中，它们又以以第二个频率除以m的时钟频率输出，以便 进一步处理。

    Concurrent asynchronous USB data stream destuffer with variable width bit-wise memory controller
    5.
    发明授权
    Concurrent asynchronous USB data stream destuffer with variable width bit-wise memory controller 失效
    并发异步USB数据流解码器，具有可变宽度位式存储器控制器

    公开(公告)号：US06883047B2

    公开(公告)日：2005-04-19

    申请号：US09866150

    申请日：2001-05-25

    申请人： Dean Warren ,  Jonathan C. Lueker

    发明人： Dean Warren ,  Jonathan C. Lueker

    IPC分类号： H03M5/14 ,  G06F13/14

    CPC分类号： G06F13/1678 ,  G06F2213/0042 ,  H03M5/14

    摘要： A concurrent asynchronous USB 2.0 data stream destuffer and separator with variable-width bit-wise memory controller is described. A parallel stream bit destuffer module identifies in parallel one or more stuffed bits in a decoded data field of a received data stream using a six-bit sliding window. The stuffed bits are bits that were inserted into the received USB data stream by a transmitter to force data transitions in the received USB data stream. A data separator module separates the one or more stuffed bits from a plurality of valid data bits in the decoded data field. A memory module generates an incremental pointer value representative of the number of valid bits and writes the plurality of valid data bits from the decoded data field into a variable sized bit-wise memory structure.

    摘要翻译： 描述了具有可变宽度逐位存储器控制器的并发异步USB 2.0数据流解压缩器和分离器。 并行流位解码器模块使用六位滑动窗口并行地识别接收数据流的解码数据字段中的一个或多个填充比特。 填充位是由发送器插入到接收的USB数据流中的位，以迫使所接收的USB数据流中的数据转换。 数据分离器模块将解码数据字段中的一个或多个填充比特从多个有效数据比特中分离出来。 存储器模块产生代表有效位数的增量指针值，并将多个有效数据位从解码数据字段写入可变大小的位逐位存储器结构。

    Data synchronization interface
    6.
    发明授权
    Data synchronization interface 失效

    公开(公告)号：US06647444B2

    公开(公告)日：2003-11-11

    申请号：US09750091

    申请日：2000-12-29

    申请人： Jonathan C. Lueker ,  Dean Warren

    发明人： Jonathan C. Lueker ,  Dean Warren

    IPC分类号： G06F1314

    CPC分类号： H04L7/02 ,  G06F5/00

    摘要： Incoming serial data which is received M bits at a time where M=N, N+1 or N−1 and N is greater than 1 is synchronized to a local clock by receiving a first M bits of data, storing the first M bits, receiving M additional bits, storing the M additional bits, repetitively receiving and storing until at least a predetermined number R of bits have been stored, where R=(M*X)+1 where X is an integer greater than one. When this occurs, the first R bits are output and any remaining S bits in excess of R are stored and additional groups of M bits added, with the process continuing until all of a packet has been received. With this arrangement, the R bits may be output at a rate which is a fraction of the serial bit rate.

    CONCURRENT ASYNCHRONOUS USB DATA STREAM DESTUFFER WITH VARIABLE WIDTH BIT-WISE MEMORY CONTROLLER
    7.
    发明申请
    CONCURRENT ASYNCHRONOUS USB DATA STREAM DESTUFFER WITH VARIABLE WIDTH BIT-WISE MEMORY CONTROLLER 审中-公开
    具有可变宽度位智能存储器控制器的同步异步USB数据流解决方案

    公开(公告)号：US20090222601A1

    公开(公告)日：2009-09-03

    申请号：US12233189

    申请日：2008-09-18

    申请人： Dean Warren ,  Jonathan C. Lueker

    发明人： Dean Warren ,  Jonathan C. Lueker

    IPC分类号： G06F13/38 ,  G06F13/42

    CPC分类号： G06F13/1678 ,  G06F2213/0042 ,  H03M5/14

    摘要： A concurrent asynchronous USB 2.0 data stream destuffer and separator with variable-width bit-wise memory controller is described. A parallel stream bit destuffer module identifies in parallel one or more stuffed bits in a decoded data field of a received data stream using a six-bit sliding window. The stuffed bits are bits that were inserted into the received USB data stream by a transmitter to force data transitions in the received USB data stream. A data separator module separates the one or more stuffed bits from a plurality of valid data bits in the decoded data field. A memory module generates an incremental pointer value representative of the number of valid bits and writes the plurality of valid data bits from the decoded data field into a variable sized bit-wise memory structure.

    摘要翻译： 描述了具有可变宽度逐位存储器控制器的并发异步USB 2.0数据流解压缩器和分离器。 并行流位解码器模块使用六位滑动窗口并行地识别接收数据流的解码数据字段中的一个或多个填充比特。 填充位是由发送器插入到接收的USB数据流中的位，以迫使所接收的USB数据流中的数据转换。 数据分离器模块将解码数据字段中的一个或多个填充比特从多个有效数据比特中分离出来。 存储器模块产生代表有效位数的增量指针值，并将多个有效数据位从解码数据字段写入可变大小的位逐位存储器结构。

    Polymer de-imprint circuit using negative voltage
    9.
    发明授权
    Polymer de-imprint circuit using negative voltage 有权
    聚合物压印电路使用负电压

    公开(公告)号：US07218545B2

    公开(公告)日：2007-05-15

    申请号：US10973580

    申请日：2004-10-25

    申请人： Jonathan C. Lueker ,  Richard L Coulson

    发明人： Jonathan C. Lueker ,  Richard L Coulson

    IPC分类号： G11C11/22

    CPC分类号： G11C29/021 ,  G11C11/22 ,  G11C29/02 ,  G11C29/028

    摘要： Briefly, voltages to write a memory cell are adjusted if the memory cell is determined to be imprinted. In one embodiment, a positive voltage not including zero is applied to one of a bit line and a word line and a negative voltage not including zero is applied to another of the bit line and the word line to write a specified logic state to an imprinted memory cell. Neighboring cells do not receive disturb voltages in excess of a disturb voltage threshold.

    摘要翻译： 简而言之，如果确定存储单元被打印，则调整写入存储器单元的电压。 在一个实施例中，将不包括零的正电压施加到位线和字线中的一个，并且不包括零的负电压被施加到位线和字线中的另一个以将指定的逻辑状态写入到印刷 记忆单元 相邻单元不会接收超过干扰电压阈值的干扰电压。

    Temperature adaptive ferro-electric memory access parameters
    10.
    发明授权
    Temperature adaptive ferro-electric memory access parameters 有权
    温度自适应铁电存储器访问参数

    公开(公告)号：US07222052B2

    公开(公告)日：2007-05-22

    申请号：US10877914

    申请日：2004-06-25

    申请人： Richard L. Coulson ,  Jonathan C. Lueker

    发明人： Richard L. Coulson ,  Jonathan C. Lueker

    IPC分类号： G06F11/30

    CPC分类号： G11C11/22

    摘要： Briefly, one or more memory access parameters used to access a memory cell are adjusted based on a sensed operating temperature. In one embodiment, a pulse width of an access voltage is increased as the operating temperature decreases below a threshold. In another embodiment, a drive voltage is decreased as the operating temperature increases.

    摘要翻译： 简而言之，基于感测到的工作温度来调整用于访问存储器单元的一个或多个存储器访问参数。 在一个实施例中，当操作温度降低到阈值以下时，存取电压的脉冲宽度增加。 在另一实施例中，驱动电压随着工作温度的升高而降低。