公开(公告)号：US06990025B2

公开(公告)日：2006-01-24

申请号：US10604994

申请日：2003-08-29

申请人： Toshiaki Kirihata ,  Hoki Kim ,  Matthew Wordeman

发明人： Toshiaki Kirihata ,  Hoki Kim ,  Matthew Wordeman

IPC分类号： G11C7/00

CPC分类号： G11C11/405 ,  G11C8/16 ,  G11C11/4099

摘要： A multi-port memory architecture utilizing an open bitline configuration for the read bitline is described. The memory is sub-divided into two arrays (A and B) consisting of memory gain cells arranged in a matrix formation, the cells having two general ports or separate read and write ports to enable simultaneous a read and write operation. Each memory array includes a reference wordline coupled to reference cells. When the reference cell is accessed, the read bitline (RBL) discharges to a level at half the value taken by a cell storing a 0 or 1. Each pair of RBLB in the same column of the two arrays is coupled to a differential sense amplifier, and each write bitline (WBL) in the two arrays is linked to write drivers WBLs in the two arrays are driven to the same voltage and at the same slew rate. The WBL swing in each array creates coupling noise by the bitline-to-bitline capacitors. For a given sense amplifier and its associated RBLs, the coupling creates an identical coupling noise on RBLA and RBLB that are positioned in the two arrays A and B. This common mode noise is rejected by the differential sense amplifier. Thus, a read sense amplifier can accurately discriminate between the signal by activating the cell by way of RWL, and the reference cell by way of REFWL.

摘要翻译： 描述了利用读取位线的开放位线配置的多端口存储器架构。 存储器被细分为由矩阵形式排列的存储器增益单元组成的两个阵列（A和B），这些单元具有两个通用端口或单独的读取和写入端口，以实现读写操作。 每个存储器阵列包括耦合到参考单元的参考字线。 当参考单元被访问时，读位线（RBL）放电到由存储0或1的单元取得的值的一半的电平上。两个阵列的同一列中的每对RBLB耦合到差分读出放大器 ，并且两个阵列中的每个写入位线（WBL）链接到写入驱动器，两个阵列中的WBLs被驱动到相同的电压和相同的转换速率。 每个阵列中的WBL摆幅通过位线到位线电容产生耦合噪声。 对于给定的读出放大器及其相关联的RBL，耦合在位于两个阵列A和B中的RBLA和RBLB上产生相同的耦合噪声。这种共模噪声被差分读出放大器拒绝。 因此，读出读出放大器可以通过RWL通过激活单元以及通过REFWL来使参考单元精确地区分信号。

公开(公告)号：US20050047218A1

公开(公告)日：2005-03-03

申请号：US10604994

申请日：2003-08-29

申请人： Toshiaki Kirihata ,  Hoki Kim ,  Matthew Wordeman

发明人： Toshiaki Kirihata ,  Hoki Kim ,  Matthew Wordeman

IPC分类号： G11C5/00 ,  G11C8/16 ,  G11C11/405 ,  G11C11/4099

CPC分类号： G11C11/405 ,  G11C8/16 ,  G11C11/4099

摘要： A multi-port memory architecture utilizing an open bitline configuration for the read bitline is described. The memory is sub-divided into two arrays (A and B) consisting of memory gain cells arranged in a matrix formation, the cells having two general ports or separate read and write ports to enable simultaneous a read and write operation. Each memory array includes a reference wordline coupled to reference cells. When the reference cell is accessed, the read bitline (RBL) discharges to a level at half the value taken by a cell storing a 0 or 1. Each pair of RBLB in the same column of the two arrays is coupled to a differential sense amplifier, and each write bitline (WBL) in the two arrays is linked to write drivers WBLs in the two arrays are driven to the same voltage and at the same slew rate. The WBL swing in each array creates coupling noise by the bitline-to-bitline capacitors. For a given sense amplifier and its associated RBLs, the coupling creates an identical coupling noise on RBLA and RBLB that are positioned in the two arrays A and B. This common mode noise is rejected by the differential sense amplifier. Thus, a read sense amplifier can accurately discriminate between the signal by activating the cell by way of RWL, and the reference cell by way of REFWL.

摘要翻译： 描述了利用读取位线的开放位线配置的多端口存储器架构。 存储器被细分为由矩阵形式排列的存储器增益单元组成的两个阵列（A和B），这些单元具有两个通用端口或单独的读取和写入端口，以实现读写操作。 每个存储器阵列包括耦合到参考单元的参考字线。 当参考单元被访问时，读位线（RBL）放电到由存储0或1的单元取得的值的一半的电平上。两个阵列的同一列中的每对RBLB耦合到差分读出放大器 ，并且两个阵列中的每个写入位线（WBL）链接到写入驱动器，两个阵列中的WBLs被驱动到相同的电压和相同的转换速率。 每个阵列中的WBL摆幅通过位线到位线电容产生耦合噪声。 对于给定的读出放大器及其相关联的RBL，耦合在位于两个阵列A和B中的RBLA和RBLB上产生相同的耦合噪声。这种共模噪声被差分读出放大器拒绝。 因此，读出读出放大器可以通过RWL通过激活单元以及通过REFWL来使参考单元精确地区分信号。

公开(公告)号：US06829682B2

公开(公告)日：2004-12-07

申请号：US09843504

申请日：2001-04-26

申请人： Toshiaki Kirihata ,  Sang Hoo Dhong ,  Hwa-Joon Oh ,  Matthew Wordeman

发明人： Toshiaki Kirihata ,  Sang Hoo Dhong ,  Hwa-Joon Oh ,  Matthew Wordeman

IPC分类号： G06F1200

CPC分类号： G06F12/0893 ,  G11C7/1006 ,  G11C2207/2245

摘要： A method for controlling the operation of a dynamic random access memory (DRAM) system, the DRAM system having a plurality of memory cells organized into rows and columns, is disclosed. In an exemplary embodiment of the invention, the method includes enabling a destructive read mode, the destructive read mode for destructively reading a bit of information stored within an addressed DRAM memory cell. The destructively read bit of information is temporarily stored into a temporary storage device. A delayed write back mode is enabled, the delayed write back mode for restoring the bit of information back to the addressed DRAM memory cell at a later time. The execution of the delayed write back mode is then scheduled, depending upon the availability of space within the temporary storage device.

摘要翻译： 公开了一种用于控制动态随机存取存储器（DRAM）系统的操作的方法，该DRAM系统具有被组织成行和列的多个存储单元。 在本发明的示例性实施例中，该方法包括启用破坏性读取模式，该破坏性读取模式用于破坏性地读取存储在寻址的DRAM存储器单元中的位的位。 信息的破坏性读取位被临时存储到临时存储设备中。 延迟回写模式被使能，延迟回写模式用于将信息位在稍后的时间恢复到寻址的DRAM存储器单元。 然后根据临时存储设备内的空间的可用性来调度延迟写回模式的执行。

公开(公告)号：US20050193253A1

公开(公告)日：2005-09-01

申请号：US10708184

申请日：2004-02-13

申请人： Jonathan Fales ,  Gregory Fredeman ,  Kevin Gorman ,  Mark Jacunski ,  Toshiaki Kirihata ,  Alan Norris ,  Paul Parries ,  Matthew Wordeman

发明人： Jonathan Fales ,  Gregory Fredeman ,  Kevin Gorman ,  Mark Jacunski ,  Toshiaki Kirihata ,  Alan Norris ,  Paul Parries ,  Matthew Wordeman

IPC分类号： G06F11/00 ,  G11C29/14 ,  G11C29/16

CPC分类号： G11C29/16 ,  G11C29/12015 ,  G11C29/14 ,  G11C2029/0401

摘要： Disclosed is a flexible command multiplication scheme for the built-in-self test (BIST) of a high-speed embedded memory array that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A stand-alone BIST logic controller operates at a lower frequency and communicates with a command multiplier using a low-speed BIST instruction seed set. The command multiplier uses offset or directive registers to drive a logic unit or ALU to generate “n” sets of CAD information which are then time-multiplexed to the embedded memory at a speed “n” times faster than the BIST operating speed.

摘要翻译： 公开了用于高速嵌入式存储器阵列的内置自检（BIST）的灵活的命令乘法方案，其将BIST功能分段成远程低速可执行指令和本地较高速可执行指令。 独立的BIST逻辑控制器以较低的频率工作，并与使用低速BIST指令种子集的命令乘法器进行通信。 命令乘法器使用偏移或指令寄存器来驱动逻辑单元或ALU以产生“n”组CAD信息，然后以比BIST操作速度快n倍的速度将时间复用到嵌入式存储器。

公开(公告)号：US20050180230A1

公开(公告)日：2005-08-18

申请号：US10777596

申请日：2004-02-12

申请人： Gregory Fredeman ,  Mark Jacunski ,  Toshiaki Kirihata ,  Matthew Wordeman

发明人： Gregory Fredeman ,  Mark Jacunski ,  Toshiaki Kirihata ,  Matthew Wordeman

IPC分类号： G11C7/00 ,  G11C29/00 ,  G11C29/40 ,  G11C29/44

CPC分类号： G11C29/4401 ,  G11C29/40 ,  G11C29/44 ,  G11C29/808 ,  G11C2029/0401 ,  G11C2029/2602

摘要： A method for allocating redundancies during a multi-bank operation in a memory device which includes two or more redundancy domains is described. The method includes steps of enabling a pass/fail bit detection to activate a given bank. The pass/fail bit detection is prompted only for a selected domain and is disabled when it addresses other domains. By altering the domain selection, it is possible to enable a redundancy allocation for any domain regardless of the multi-bank operation. The method may preferably be realized by using a dynamic exclusive-OR logic with true and complement expected data pairs. When combined with simple pointer logic, the selection of domains may be generated internally, simplifying the built in self-test and other test control protocols, while at the same time tracking those that fail.

摘要翻译： 描述了在包括两个或更多个冗余域的存储器设备中在多存储体操作期间分配冗余的方法。 该方法包括启用通过/故障位检测来激活给定的存储体的步骤。 通过/失败位检测仅对选定的域提示，并且在寻址其他域时被禁用。 通过改变域选择，无论多行操作如何，都可以为任何域启用冗余分配。 该方法可以优选地通过使用具有真实和补充预期数据对的动态异或逻辑来实现。 当结合简单的指针逻辑时，可以内部生成域的选择，简化内置的自检和其他测试控制协议，同时跟踪失败的那些。

公开(公告)号：US20060285411A1

公开(公告)日：2006-12-21

申请号：US11160273

申请日：2005-06-16

申请人： Hoki Kim ,  Toshiaki Kirihata

发明人： Hoki Kim ,  Toshiaki Kirihata

IPC分类号： G11C7/00

CPC分类号： G11C11/4097 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/18 ,  G11C8/10 ,  G11C8/16 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/4094

摘要： A multi-port DRAM having refresh cycles interleaved with normal read and write operations implements a single cycle refresh sequence by deferring the write portion of the sequence until the next refresh cycle. During a single clock cycle, the system writes stored data from a refresh buffer into a row in the memory array and then reads data from one row of the memory array into the buffer.

摘要翻译： 具有与正常读取和写入操作交织的刷新周期的多端口DRAM通过推迟序列的写入部分直到下一个刷新周期来实现单周期刷新序列。 在单个时钟周期内，系统将存储的数据从刷新缓冲区写入存储器阵列中的一行，然后将数据从存储器阵列的一行读入缓冲区。

公开(公告)号：US07145829B1

公开(公告)日：2006-12-05

申请号：US11160273

申请日：2005-06-16

申请人： Hoki Kim ,  Toshiaki Kirihata

发明人： Hoki Kim ,  Toshiaki Kirihata

IPC分类号： C11C7/00

CPC分类号： G11C11/4097 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/18 ,  G11C8/10 ,  G11C8/16 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/4094

摘要： A multi-port DRAM having refresh cycles interleaved with normal read and write operations implements a single cycle refresh sequence by deferring the write portion of the sequence until the next refresh cycle. During a single clock cycle, the system writes stored data from a refresh buffer into a row in the memory array and then reads data from one row of the memory array into the buffer.

摘要翻译： 具有与正常读取和写入操作交错的刷新周期的多端口DRAM通过推迟序列的写入部分直到下一个刷新周期来实现单周期刷新序列。 在单个时钟周期内，系统将存储的数据从刷新缓冲区写入存储器阵列中的一行，然后将数据从存储器阵列的一行读入缓冲区。

公开(公告)号：US20090103390A1

公开(公告)日：2009-04-23

申请号：US11875173

申请日：2007-10-19

申请人： Hoki Kim ,  Toshiaki Kirihata

发明人： Hoki Kim ,  Toshiaki Kirihata

IPC分类号： G11C8/00

CPC分类号： G11C8/16 ,  G11C7/02 ,  G11C7/1075 ,  G11C7/18 ,  G11C11/412

摘要： Embodiments of the present invention provide a memory array of dual part cells and design structure thereof. The memory array has a pair of twisted write bit lines and a pair of twisted read bit lines for each column. The twist is made by alternating the vertical position of each bit line pair in each section of a column, with the result of generating common mode nose and of reducing differential mode noise.

摘要翻译： 本发明的实施例提供了双重部分单元的存储器阵列及其设计结构。 存储器阵列具有一对扭曲的写位线和用于每列的一对扭转的读位线。 通过在列的每个部分中交替每个位线对的垂直位置来进行扭转，从而产生共模鼻子并且减小差模噪声。

公开(公告)号：US07885138B2

公开(公告)日：2011-02-08

申请号：US11875173

申请日：2007-10-19

申请人： Hoki Kim ,  Toshiaki Kirihata

发明人： Hoki Kim ,  Toshiaki Kirihata

IPC分类号： G11C8/00

CPC分类号： G11C8/16 ,  G11C7/02 ,  G11C7/1075 ,  G11C7/18 ,  G11C11/412

摘要： Embodiments of the present invention provide a memory array of dual part cells and design structure thereof. The memory array has a pair of twisted write bit lines and a pair of twisted read bit lines for each column. The twist is made by alternating the vertical position of each bit line pair in each section of a column, with the result of generating common mode nose and of reducing differential mode noise.

摘要翻译： 本发明的实施例提供了双重部分单元的存储器阵列及其设计结构。 存储器阵列具有一对扭曲的写位线和用于每列的一对扭转的读位线。 通过在列的每个部分中交替每个位线对的垂直位置来进行扭转，从而产生共模鼻子并且减小差模噪声。

公开(公告)号：US06954387B2

公开(公告)日：2005-10-11

申请号：US10604375

申请日：2003-07-15

申请人： Hoki Kim ,  Toshiaki Kirihata ,  David R. Hanson ,  Gregory J. Fredeman ,  John Golz

发明人： Hoki Kim ,  Toshiaki Kirihata ,  David R. Hanson ,  Gregory J. Fredeman ,  John Golz

IPC分类号： G11C11/406 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C11/40618 ,  G11C11/406 ,  G11C2207/104

摘要： In a DRAM, which includes a plurality of memory banks, there is a pair of separate flag bit registers for each bank with the flag bit registers that are shifted up/down respectively. A comparator for each bank provides a comparator output. An arbiter for each bank is connected to receive a flag bit up signal and a flag bit down signal from the flag bit registers for that bank and the comparator output from the comparator for that bank. The arbiters are connected to receive a conflict in signal and to provide a conflict out signal. The pair of flag bit registers represent a refresh status of each bank and designate memory banks or arrays that are ready for a refresh operation.

摘要翻译： 在包括多个存储体的DRAM中，对于每个存储体，存在分别向上/向下移位的标志位寄存器的一对分离的标志位寄存器。 每个组的比较器提供一个比较器输出。 每个存储体的仲裁器被连接以从该存储体的标志位寄存器和对于该存储体的比较器输出的比较器输出标志位向上信号和标志位降低信号。 仲裁器被连接以接收信号中的冲突并提供冲突信号。 一对标志位寄存器表示每个存储体的刷新状态，并指定准备进行刷新操作的存储体或阵列。