公开(公告)号：US07068652B2

公开(公告)日：2006-06-27

申请号：US10090797

申请日：2002-03-06

申请人： Jonathan Lin ,  Somayajulu Pullela ,  David Billings

发明人： Jonathan Lin ,  Somayajulu Pullela ,  David Billings

IPC分类号： H04J1/16

CPC分类号： H04L41/0893 ,  H04L47/2441

摘要： A network device includes at least one network port, a masks table, a rules table, a pointers table, and a fast filter processor. The masks table contains filter information and a mask key. The rules table contains corresponding rules to the filter information and is related to the mask table by the mask key. The pointers table contains boundary data related to the rules for corresponding filter information. The fast filter processor is coupled to the mask table, the rules table and the pointers table, and configured to perform at least one binary search for at least one rule related to a data packet received by the network device at the at least one network port, the binary search being limited based on the boundary data in the pointers table.

公开(公告)号：US06813620B2

公开(公告)日：2004-11-02

申请号：US10083591

申请日：2002-02-27

申请人： Jonathan Lin ,  David Billings ,  Mike Jorda

发明人： Jonathan Lin ,  David Billings ,  Mike Jorda

IPC分类号： G06F1730

CPC分类号： G06F17/30946 ,  Y10S707/99933 ,  Y10S707/99938

摘要： A network device including a memory, a queue management unit, a memory management unit, and a search switching unit. The memory includes a plurality of memory banks. The queue management unit is configured to receive a plurality of search requests and to prioritize the search requests. The memory management unit is coupled to the queue management unit and the memory, and is configured to initiate a plurality of binary searches based on the plurality of search requests. Each binary search is executed simultaneously in different banks of the plurality of memory banks. The search switching unit is coupled to the memory and the memory management unit, and is configured to switch each binary search from one memory bank of to another memory bank after a predetermined number of search steps are performed by each binary search.

摘要翻译： 一种网络设备，包括存储器，队列管理单元，存储器管理单元和搜索切换单元。 存储器包括多个存储体。 队列管理单元被配置为接收多个搜索请求并且优先处理搜索请求。 存储器管理单元耦合到队列管理单元和存储器，并且被配置为基于多个搜索请求发起多个二进制搜索。 在多个存储体的不同的存储体中同时执行每个二进制搜索。 搜索切换单元耦合到存储器和存储器管理单元，并且被配置为在通过每个二进制搜索执行预定数量的搜索步骤之后将每个二进制搜索从一个存储体切换到另一个存储体。

公开(公告)号：US06965945B2

公开(公告)日：2005-11-15

申请号：US10083132

申请日：2002-02-27

申请人： Jonathan Lin ,  David Billings

发明人： Jonathan Lin ,  David Billings

IPC分类号： H04L12/56 ,  G06F15/173

CPC分类号： H04L45/742 ,  H04L49/3018 ,  H04L49/351 ,  H04L49/354 ,  Y10S707/99933

摘要： A network device including at least one network port, a clock, address resolution (ARL) tables, and address resolution logic. The at least one network port is configured to send and receive a data packet. The clock is for generating a timing signal. The ARL tables are configured to store and maintain data related to port addresses of the network device. The address resolution logic is coupled to the ARL tables and configured to perform a search and an update to data into the ARL tables based on the data packet, to calculate a current range of the search, to determine an intended result of the update, and to block the update when the intended result will move data out of the current range of the search, the search and the update being performed concurrently during alternating slots of the timing signal.

摘要翻译： 包括至少一个网络端口，时钟，地址解析（ARL）表和地址解析逻辑的网络设备。 所述至少一个网络端口被配置为发送和接收数据分组。 时钟用于产生定时信号。 ARL表被配置为存储和维护与网络设备的端口地址相关的数据。 地址解析逻辑耦合到ARL表并且被配置为基于数据分组来执行对ARL表的数据的搜索和更新，以计算搜索的当前范围，以确定更新的预期结果，以及 当预期结果将数据移出搜索的当前范围时，阻止更新，搜索和更新在定时信号的交替时隙期间同时执行。

公开(公告)号：US20050076035A1

公开(公告)日：2005-04-07

申请号：US10965728

申请日：2004-10-18

申请人： Jonathan Lin ,  David Billings ,  Mike Jorda

发明人： Jonathan Lin ,  David Billings ,  Mike Jorda

IPC分类号： G06F17/30

CPC分类号： G06F17/30946 ,  Y10S707/99933 ,  Y10S707/99938

摘要： A network device including a memory, a queue management unit, a memory management unit, and a search switching unit. The memory includes a plurality of memory banks. The queue management unit is configured to receive a plurality of search requests and to prioritize the search requests. The memory management unit is coupled to the queue management unit and the memory, and is configured to initiate a plurality of binary searches based on the plurality of search requests. Each binary search is executed simultaneously in different banks of the plurality of memory banks. The search switching unit is coupled to the memory and the memory management unit, and is configured to switch each binary search from one memory bank of to another memory bank after a predetermined number of search steps are performed by each binary search.

摘要翻译： 一种网络设备，包括存储器，队列管理单元，存储器管理单元和搜索切换单元。 存储器包括多个存储体。 队列管理单元被配置为接收多个搜索请求并且优先处理搜索请求。 存储器管理单元耦合到队列管理单元和存储器，并且被配置为基于多个搜索请求发起多个二进制搜索。 在多个存储体的不同的存储体中同时执行每个二进制搜索。 搜索切换单元耦合到存储器和存储器管理单元，并且被配置为在通过每个二进制搜索执行预定数量的搜索步骤之后将每个二进制搜索从一个存储体切换到另一个存储体。

公开(公告)号：US06981058B2

公开(公告)日：2005-12-27

申请号：US10083594

申请日：2002-02-27

申请人： Jonathan Lin ,  David Billings

发明人： Jonathan Lin ,  David Billings

IPC分类号： H04L12/56 ,  H04L29/06 ,  H04L29/12 ,  G06F15/173

CPC分类号： H04L29/12009 ,  H04L29/12018 ,  H04L29/12924 ,  H04L45/36 ,  H04L49/109 ,  H04L61/10 ,  H04L61/6063 ,  Y10S707/99933

摘要： A network device including at least one network port, a clock, address resolution logic (ARL) tables, and address resolution logic. The clock generates a timing signal. The ARL tables are configured to store and maintain data related to port addresses of the network device. The address resolution logic is coupled to the ARL tables and the clock, and configured to search the ARL tables and to perform learning concurrently during alternating slots of the timing signal. Upon receiving a data packet at the at least one port, the address resolution logic is configured to search the ARL tables for a destination address based on the data packet. When the destination address is found, the address resolution logic is configured to update a related record of the ARL tables based on the learning, the address resolution logic configured to perform searches and updates.

摘要翻译： 包括至少一个网络端口，时钟，地址解析逻辑（ARL）表和地址解析逻辑的网络设备。 时钟产生定时信号。 ARL表被配置为存储和维护与网络设备的端口地址相关的数据。 地址解析逻辑耦合到ARL表和时钟，并被配置为搜索ARL表并在定时信号的交替时隙期间同时执行学习。 在所述至少一个端口处接收到数据分组时，所述地址解析逻辑被配置为基于所述数据分组来搜索所述ARL表中的目的地地址。 当找到目的地地址时，地址解析逻辑被配置为基于学习，被配置为执行搜索和更新的地址解析逻辑来更新ARL表的相关记录。

公开(公告)号：US07010535B2

公开(公告)日：2006-03-07

申请号：US10965728

申请日：2004-10-18

申请人： Jonathan Lin ,  David Billings ,  Mike Jorda

发明人： Jonathan Lin ,  David Billings ,  Mike Jorda

IPC分类号： G06F17/30

CPC分类号： G06F17/30946 ,  Y10S707/99933 ,  Y10S707/99938

摘要： A network device including a memory, a queue management unit, a memory management unit, and a search switching unit. The memory includes a plurality of memory banks. The queue management unit is configured to receive a plurality of search requests and to prioritize the search requests. The memory management unit is coupled to the queue management unit and the memory, and is configured to initiate a plurality of binary searches based on the plurality of search requests. Each binary search is executed simultaneously in different banks of the plurality of memory banks. The search switching unit is coupled to the memory and the memory management unit, and is configured to switch each binary search from one memory bank of to another memory bank after a predetermined number of search steps are performed by each binary search.

公开(公告)号：US20080030716A1

公开(公告)日：2008-02-07

申请号：US11804593

申请日：2007-05-18

申请人： Thomas Jeys ,  Antonio Sanchez-Rubio ,  Ronald Hoffeld ,  Jonathan Lin ,  Nicholas Judson ,  George Haldeman ,  Vincenzo Daneu

发明人： Thomas Jeys ,  Antonio Sanchez-Rubio ,  Ronald Hoffeld ,  Jonathan Lin ,  Nicholas Judson ,  George Haldeman ,  Vincenzo Daneu

IPC分类号： G01N21/00 ,  G06F19/00

CPC分类号： G01N21/53 ,  G01B11/002 ,  G01N15/1459 ,  G01N2015/145

摘要： Aerosol and hydrosol particle detection systems without knowledge of a location and velocity of a particle passing through a volume of space, are less efficient than if knowledge of the particle location is known. An embodiment of a particle position detection system capable of determining an exact location of a particle in a fluid stream is discussed. The detection system may employ a patterned illuminating beam, such that once a particle passes through the patterned illuminating beam, a light scattering is produced. The light scattering defines a temporal profile that contains measurement information indicative of an exact particle location. However, knowledge of the exact particle location has several advantages. These advantages include correction of systematic particle measurement errors due to variability of the particle position within the sample volume, targeting of particles based on position, capture of particles based on position, reduced system energy consumption and reduced system complexity.

摘要翻译： 没有了解通过一定空间的颗粒的位置和速度的气溶胶和水溶胶颗粒检测系统比知道颗粒位置的知识效率低。 讨论了能够确定流体流中颗粒的确切位置的粒子位置检测系统的实施例。 检测系统可以使用图案化的照明光束，使得一旦粒子通过图案化的照明光束，就产生光散射。 光散射定义了包含指示精确粒子位置的测量信息的时间曲线。 然而，确切的粒子位置的知识有几个优点。 这些优点包括校正由于样品体积内的颗粒位置的变异性引起的系统的颗粒测量误差，基于位置的颗粒靶向，基于位置的颗粒捕获，降低的系统能量消耗和降低的系统复杂性。

公开(公告)号：US07308568B2

公开(公告)日：2007-12-11

申请号：US11580956

申请日：2006-10-16

申请人： Jonathan Lin ,  Yong Jiang

发明人： Jonathan Lin ,  Yong Jiang

IPC分类号： G03F7/38

CPC分类号： G06F13/385 ,  H03L7/0812 ,  H04J3/0697 ,  H04L49/351 ,  H04L49/352 ,  H04L49/354 ,  H04L49/40

摘要： A network device is provided which includes a device input, at least one port, a frequency doubler, a data I/O device, and a programmable delay locked loop. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal having double the frequency of the input signal. The data I/O device is configured to output data based upon a reference clock signal. The programmable delay locked loop is coupled to the device input and configured to receive an input signal and to automatically output an output signal being a predetermined amount out of phase from the input signal. An external clock signal received at the device input is input to the frequency doubler. The output of the frequency doubler is input to the data I/O device as a reference clock. Data (e.g., from internal device logic) is output from the data I/O device to the at least one port. The external clock signal is input to the programmable delay locked loop, which outputs an output clock signal having a frequency equal to the frequency of the external clock signal, in synchronization with the data being output.

摘要翻译： 提供一种网络设备，其包括设备输入，至少一个端口，倍频器，数据I / O设备和可编程延迟锁定环路。 倍频器耦合到输入并被配置为接收输入信号并输出​​具有输入信号频率的两倍的输出信号。 数据I / O设备被配置为基于参考时钟信号输出数据。 可编程延迟锁定环路耦合到设备输入端并被配置为接收输入信号并自动输出来自输入信号的异相预定量的输出信号。 在器件输入端接收的外部时钟信号输入倍频器。 倍频器的输出作为参考时钟输入到数据I / O设备。 数据（例如，从内部设备逻辑）从数据I / O设备输出到至少一个端口。 外部时钟信号被输入到可编程延迟锁定环路，与输出的数据同步地输出具有等于外部时钟信号频率的频率的输出时钟信号。

公开(公告)号：US20070055794A1

公开(公告)日：2007-03-08

申请号：US11164777

申请日：2005-12-05

申请人： Willy Chuang ,  Jakie Yeh ,  Shangen Wang ,  Jonathan Lin

发明人： Willy Chuang ,  Jakie Yeh ,  Shangen Wang ,  Jonathan Lin

IPC分类号： G06F3/00

CPC分类号： G06F8/65

摘要： Firmware of an optical storage medium device includes an executable program code and at least one reference data set. A method for modifying the firmware without requiring a compiling process includes inputting an attribute data set for setting a user interface; modifying the firmware by modifying the reference data set according to the attribute data set, wherein the executable program code is not modified when the firmware is being modified; determining if the modified firmware is capable of performing a target operation before the modified firmware is written into the optical storage medium device, wherein the user interface can be displayed according to the attribute data set; displaying the user interface according to the attribute data set; and writing the modified firmware into the optical storage medium device after the modified firmware is capable of performing the target operation.

摘要翻译： 光学存储介质设备的固件包括可执行程序代码和至少一个参考数据集。 一种用于在不需要编译过程的情况下修改固件的方法包括：输入用于设置用户界面的属性数据集; 通过根据属性数据集修改参考数据集来修改固件，其中当修改固件时，不修改可执行程序代码; 在修改的固件被写入光存储介质设备之前，确定修改的固件是否能够执行目标操作，其中可以根据属性数据集来显示用户界面; 根据属性数据集显示用户界面; 以及在修改的固件能够执行目标操作之后将修改的固件写入光存储介质设备。

公开(公告)号：US06920552B2

公开(公告)日：2005-07-19

申请号：US10083291

申请日：2002-02-27

申请人： Jonathan Lin ,  Yong Jiang

发明人： Jonathan Lin ,  Yong Jiang

IPC分类号： H03L7/081 ,  H04J3/06 ,  H04L12/56 ,  G03F7/38

CPC分类号： G06F13/385 ,  H03L7/0812 ,  H04J3/0697 ,  H04L49/351 ,  H04L49/352 ,  H04L49/354 ,  H04L49/40

摘要： A network device is provided which includes a device input, at least one port, a frequency doubler, a data I/O device, and a programmable delay locked loop. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal having double the frequency of the input signal. The data I/O device is configured to output data based upon a reference clock signal. The programmable delay locked loop is coupled to the device input and configured to receive an input signal and to automatically output an output signal being a predetermined amount out of phase from the input signal. An external clock signal received at the device input is input to the frequency doubler. The output of the frequency doubler is input to the data I/O device as a reference clock. Data (e.g., from internal device logic) is output from the data I/O device to the at least one port. The external clock signal is input to the programmable delay locked loop, which outputs an output clock signal having a frequency equal to the frequency of the external clock signal, in synchronization with the data being output.

摘要翻译： 提供一种网络设备，其包括设备输入，至少一个端口，倍频器，数据I / O设备和可编程延迟锁定环路。 倍频器耦合到输入并被配置为接收输入信号并输出​​具有输入信号频率的两倍的输出信号。 数据I / O设备被配置为基于参考时钟信号输出数据。 可编程延迟锁定环路耦合到设备输入端并被配置为接收输入信号并自动输出来自输入信号的异相预定量的输出信号。 在器件输入端接收的外部时钟信号输入倍频器。 倍频器的输出作为参考时钟输入到数据I / O设备。 数据（例如，从内部设备逻辑）从数据I / O设备输出到至少一个端口。 外部时钟信号被输入到可编程延迟锁定环路，与输出的数据同步地输出具有等于外部时钟信号频率的频率的输出时钟信号。