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    System-on-chip (SOC), design structure and method
    1.
    发明授权
    System-on-chip (SOC), design structure and method 有权
    片上系统（SOC），设计结构和方法

    公开(公告)号：US07904873B2

    公开(公告)日：2011-03-08

    申请号：US12125269

    申请日：2008-05-22

    申请人： Jonathan P. Ebbers ,  Todd E. Leonard ,  Kyle E. Schneider ,  Peter A. Twombly

    发明人： Jonathan P. Ebbers ,  Todd E. Leonard ,  Kyle E. Schneider ,  Peter A. Twombly

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F2217/66

    摘要： Disclosed is a system-on-chip (SOC) structure that allows for automated integration of multiple intellectual cores. The SOC structure incorporates a plurality of cells connected to a common bus on a chip. Each cell incorporates a functional core and an automated integration unit (AIU) connected to the functional core. Each AIU communicates integration information for its functional core over the common bus to the AIUs in the other cells. The exchange of information between the AIUs is controlled either by the integration units themselves or by a controller. Based on received integration information, each AIU can automatically make any required configuration adjustments for integration. Furthermore, based on this exchange of information, the functional cores can interact, as necessary, during SOC operation. Also disclosed are an associated method of forming such a SOC structure and a design structure for such an SOC structure.

    摘要翻译： 公开了一种片上系统（SOC）结构，允许多个智能核心的自动化集成。 SOC结构包括连接到芯片上的公共总线的多个单元。 每个单元结合功能核心和连接到功能核心的自动化集成单元（AIU）。 每个AIU通过公共总线将其功能核心的集成信息传送到其他单元中的AIU。 AIU之间的信息交换由集成单元本身或控制器控制。 基于接收的集成信息，每个AIU可以自动进行任何必要的配置调整进行集成。 此外，基于这种信息交换，功能核心可以根据需要在SOC操作期间进行交互。 还公开了形成这种SOC结构的相关方法和用于这种SOC结构的设计结构。

    System-on-chip (SOC), design structure and method
    2.
    发明授权
    System-on-chip (SOC), design structure and method 有权

    公开(公告)号：US07904872B2

    公开(公告)日：2011-03-08

    申请号：US12125255

    申请日：2008-05-22

    申请人： Jonathan P. Ebbers ,  Todd E. Leonard ,  Kyle E. Schneider ,  Peter A. Twombly

    发明人： Jonathan P. Ebbers ,  Todd E. Leonard ,  Kyle E. Schneider ,  Peter A. Twombly

    IPC分类号： G06F17/50

    CPC分类号： G06F15/7807

    摘要： Disclosed is a system-on-chip (SOC) structure that allows for automated integration of multiple intellectual cores. The SOC structure incorporates a plurality of cells connected to a common bus on a chip. Each cell incorporates a functional core and an automated integration unit (AIU) connected to the functional core. Each AIU communicates integration information for its functional core over the common bus to the AIUs in the other cells. The exchange of information between the AIUs is controlled either by the integration units themselves or by a controller. Based on received integration information, each AIU can automatically make any required configuration adjustments for integration. Furthermore, based on this exchange of information, the functional cores can interact, as necessary, during SOC operation. Also disclosed are an associated method of forming such a SOC structure and a design structure for such an SOC structure.

    System-On-Chip (SOC), Design Structure and Method
    3.
    发明申请
    System-On-Chip (SOC), Design Structure and Method 有权
    片上系统（SOC），设计结构与方法

    公开(公告)号：US20090292828A1

    公开(公告)日：2009-11-26

    申请号：US12125255

    申请日：2008-05-22

    申请人： Jonathan P Ebbers ,  Todd E. Leonard ,  Kyle E. Schneider ,  Peter A. Twombly

    发明人： Jonathan P Ebbers ,  Todd E. Leonard ,  Kyle E. Schneider ,  Peter A. Twombly

    IPC分类号： G06F3/00

    CPC分类号： G06F15/7807

    摘要： Disclosed is a system-on-chip (SOC) structure that allows for automated integration of multiple intellectual cores. The SOC structure incorporates a plurality of cells connected to a common bus on a chip. Each cell incorporates a functional core and an automated integration unit (AIU) connected to the functional core. Each AIU communicates integration information for its functional core over the common bus to the AIUs in the other cells. The exchange of information between the AIUs is controlled either by the integration units themselves or by a controller. Based on received integration information, each AIU can automatically make any required configuration adjustments for integration. Furthermore, based on this exchange of information, the functional cores can interact, as necessary, during SOC operation. Also disclosed are an associated method of forming such a SOC structure and a design structure for such an SOC structure.

    摘要翻译： 公开了一种片上系统（SOC）结构，允许多个智能核心的自动化集成。 SOC结构包括连接到芯片上的公共总线的多个单元。 每个单元结合功能核心和连接到功能核心的自动化集成单元（AIU）。 每个AIU通过公共总线将其功能核心的集成信息传送到其他单元中的AIU。 AIU之间的信息交换由集成单元本身或控制器控制。 基于接收的集成信息，每个AIU可以自动进行任何必要的配置调整进行集成。 此外，基于这种信息交换，功能核心可以根据需要在SOC操作期间进行交互。 还公开了形成这种SOC结构的相关方法和用于这种SOC结构的设计结构。

    System-On-Chip (SOC), Design Structure and Method
    4.
    发明申请
    System-On-Chip (SOC), Design Structure and Method 有权

    公开(公告)号：US20090291533A1

    公开(公告)日：2009-11-26

    申请号：US12125269

    申请日：2008-05-22

    申请人： Jonathan P. Ebbers ,  Todd E. Leonard ,  Kyle E. Schneider ,  Peter A. Twombly

    发明人： Jonathan P. Ebbers ,  Todd E. Leonard ,  Kyle E. Schneider ,  Peter A. Twombly

    IPC分类号： H01L21/77

    CPC分类号： G06F17/5045 ,  G06F2217/66

    摘要： Disclosed is a system-on-chip (SOC) structure that allows for automated integration of multiple intellectual cores. The SOC structure incorporates a plurality of cells connected to a common bus on a chip. Each cell incorporates a functional core and an automated integration unit (AIU) connected to the functional core. Each AIU communicates integration information for its functional core over the common bus to the AIUs in the other cells. The exchange of information between the AIUs is controlled either by the integration units themselves or by a controller. Based on received integration information, each AIU can automatically make any required configuration adjustments for integration. Furthermore, based on this exchange of information, the functional cores can interact, as necessary, during SOC operation. Also disclosed are an associated method of forming such a SOC structure and a design structure for such an SOC structure.

    On-chip identification circuit incorporating pairs of conductors, each having an essentially random chance of being shorted together as a result of process variations
    8.
    发明授权
    On-chip identification circuit incorporating pairs of conductors, each having an essentially random chance of being shorted together as a result of process variations 有权
    集成了导体对的片上识别电路，每个导体具有由于工艺变化而基本上随机的短路的机会

    公开(公告)号：US08291357B2

    公开(公告)日：2012-10-16

    申请号：US11869179

    申请日：2007-10-09

    申请人： Serafino Bueti ,  Adam J. Courchesne ,  Kenneth J. Goodnow ,  Todd E. Leonard ,  Peter A. Sandon ,  Peter A. Twombly ,  Charles S. Woodruff

    发明人： Serafino Bueti ,  Adam J. Courchesne ,  Kenneth J. Goodnow ,  Todd E. Leonard ,  Peter A. Sandon ,  Peter A. Twombly ,  Charles S. Woodruff

    IPC分类号： G06F9/45

    CPC分类号： H01L23/544 ,  H01L23/5286 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/00

    摘要： Disclosed are embodiments of on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors. In each embodiment the resulting pattern of shorts and opens, can be used as an on-chip identifier or private key.

    摘要翻译： 公开了片上识别电路的实施例。 在一个实施例中，在一个或多个金属化层内形成导体对（例如，金属焊盘，通孔，线）。 每对中的导体之间的距离是预先确定的，因此，在已知的跨越芯片线的变化中，存在短路的随机机会（即，大约50/50的几率）。 在另一个实施例中，不同的掩模形成第一导体（例如，由变化的距离分隔并具有不同宽度的金属线）和第二导体（例如，通过变化的距离分开并具有相等宽度的金属通孔）。 第一和第二导体在芯片之间交替。 由于第一导体的分离距离和宽度不同，第二导体的不同间隔距离和随机掩模对准变化，每个第一导体可以短至多达两个第二导体。 在每个实施例中，所得到的短路和开路模式可用作片上标识符或私钥。

    Dynamic critical path detector for digital logic circuit paths
    10.
    发明授权
    Dynamic critical path detector for digital logic circuit paths 有权
    用于数字逻辑电路路径的动态关键路径检测器

    公开(公告)号：US08132136B2

    公开(公告)日：2012-03-06

    申请号：US11937111

    申请日：2007-11-08

    申请人： Serafino Bueti ,  Kenneth J. Goodnow ,  Todd E. Leonard ,  Gregory J. Mann ,  Peter A. Sandon ,  Peter A. Twombly ,  Charles S. Woodruff

    发明人： Serafino Bueti ,  Kenneth J. Goodnow ,  Todd E. Leonard ,  Gregory J. Mann ,  Peter A. Sandon ,  Peter A. Twombly ,  Charles S. Woodruff

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further includes generating a delayed data value from the data value, latching the delayed data value in the second latch, comparing the data value with the delayed data value to determine whether the critical path comprises a timing failure condition, and executing a predetermined corrective measure for the critical path. The invention is also directed to a design structure on which a circuit resides.

    摘要翻译： 用于校正集成电路中的定时故障的方法和用于监视集成电路的装置。 该方法包括将第一和第二闩锁放置在关键路径附近。 第一锁存器具有包括关键路径上的数据值的输入。 该方法还包括从数据值产生延迟的数据值，将延迟的数据值锁存在第二锁存器中，将数据值与延迟的数据值进行比较，以确定关键路径是否包括定时失败状况，以及执行预定的校正 衡量关键路径。 本发明还涉及电路所在的设计结构。